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* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-215-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_i2c: Remove usb_i2c_board_enable/disableNicolas Boichat2017-11-201-12/+0
| | | | | | | | | | | | | | | | These functions are not used by usb_i2c.c on chip/stm32, let's move them to board/cr50 which is the only place where they are used. BRANCH=none BUG=None TEST=make buildall -j Change-Id: I8c1b292838b8dbee9a9001add9332e0add80c342 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/778749 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* touchpad_elan: Rename task/interrupts functionsNicolas Boichat2017-11-202-1/+12
| | | | | | | | | | | | | | | | | | Change the names to generic touchpad_* functions, instead of vendor-specific names. Makes it a little easier to add drivers for other touchpads. Also fix console_channel.inc to add the channel whenever any touchpad is used. BRANCH=none BUG=b:68934906 TEST=make buildall -j Change-Id: I6d268db5ebd53db272fb2ee7bbf06bbe80845734 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/778750 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-172-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion_sense: Put set_range in common codeGwendal Grignou2017-11-171-4/+4
| | | | | | | | | | | | | | | | At the end of the sensor initialization, all _init sensor routines set the range to the default value from board.c file. Put all the code in a single place, move it from sensor_common.c to motion_sense.c. BUG=none BRANCH=none TEST=compile Change-Id: If89cf27c6438e0f215c193d68a480e027110174c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767610 Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add software CTZ implementation when needeedGwendal Grignou2017-11-161-0/+3
| | | | | | | | | | | | | | | | | CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or nds32. Used in ST sensor drivers. BUG=none BRANCH=none TEST=compile Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767609 Commit-Ready: Ely Vazquez <nadia198877@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: Lower sensor max ODRGwendal Grignou2017-11-151-2/+9
| | | | | | | | | | | | | | | | EC seems to miss sample while providing sensor data at 200Hz. Limit sensors ODR to 100Hz. BUG=b:67112751 BRANCH=none TEST=compile, tbd Change-Id: Ic324c3d989854ae8b7f6b27bf6338266ce01ceda Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753434 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Add wait-ext option to ec reboot commandScott Collyer2017-11-151-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_IN_RW signal is used to determine if the switch to dev mode can be safely made. However, EC_IN_RW needs the EC_RST_L line driven low in order to be reset. In faft tests that utilize crosEcSoftrecPower method, EC_RST_L is not being driven by servo to fix other test failures related to keeping EC and AC reboots in sync. This CL adds a new argument 'wait-ext' to the EC reboot command. When this option is used, instead of the EC generating a reset via it's system watchdog, it will wait 10 seconds for EC_RST_L to be driven. BUG=b:64603944 BRANCH=coral CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode" mutliple times and verified that it passes. Previoulsy, this test always fails when the EC is in RW before it starts. Also tested platform_ServoPowerStateController_USBPluggedin and verified it passed. Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/737524 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "power: Get rid of power_board_handle_host_sleep_event"Furquan Shaikh2017-11-151-0/+8
| | | | | | | | | | | | | | | | | This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall Change-Id: I6885e7447277d853a2414be299dfea25f5547df4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771054 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* it83xx: add espi moduleDino Li2017-11-141-1/+2
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_update: Add support for touchpad debugging featureNicolas Boichat2017-11-141-0/+18
| | | | | | | | | | | | | | | | We support touchpad-specific debugging feature over the USB update protocol. This will be used to fetch raw data from the sensor, without requiring to remove the write-protect screw. BRANCH=none BUG=b:63993891 TEST=./usb_updater2 -g 00 -d 18d1:502b Change-Id: I46dfd97aaa17b73a5893fe1e8c62327a302f829b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/763574 Reviewed-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fizz: Switch power source to BJ at G3/S5Daisuke Nojiri2017-11-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This patch allows Fizz to switch the power source from a type-c charger to a barrel jack adapter if the system is in S5. BUG=b:38321259 BRANCH=none TEST=Verify the following with 45W and 60W type-c chargers: 1. Boot Fizz with a type-c charger 2. Go to S5 if not already. 3. Plug in a BJ adapter. Fizz boots to S0 using BJ power. Also verified other boot modes are not affected: 1. Auto boot on BJ insert 2. Auto boot on Type-C insert 3. Recovery boot on BJ 4. Recovery boot on Type-C 5. Stay off if it's previously S5 Change-Id: I86aa0fe6e403bcbacfe396997d897111ffcf8e74 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/706251 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* gru: Remove `flashinfo` command for RAM savingsShawn Nematbakhsh2017-11-091-0/+1
| | | | | | | | | | | | | BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ibfbb6875327dfc13dcba57933d39fd207f382ac1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/761299 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tpm: provide means of shutting down comms layer while in resetVadim Bendebury2017-11-071-3/+7
| | | | | | | | | | | | | | | | | | | | | | | Currently the Cr50 code resets TPM communications layer at a certain point during TPM reset process. It turns out that this is not sufficient - the comms layer keeps receiving and trying to invoke TPM layer, which does not mesh well with TPM reset. Let's provide two callbacks for each comms layer - to shut it down and to bring it back up. We shut down the comms when starting TPM reset and bring them back up when reset is completed. BRANCH=cr50 BUG=b:68012381 TEST=ran AP firmware test suite on both SPI and I2C based devices. Change-Id: I7caf4a09b9a5c6e5fc6bfe60eae1c0d64ab24904 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/754502 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Mark reset and panic functions as noreturnPatrick Georgi2017-11-072-3/+3
| | | | | | | | | | | | | | | | | | | gcc 6.3 (as provided by coreboot-sdk) needs that to know which code paths end early. Also add a loop after the command that is "supposed" to reset the machine so that the compiler believes it (and in case that assumption fails). BRANCH=none BUG=b:65441143 TEST=none Change-Id: Idb87253ec7880d66ffec30d75f4d007f02f63aab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/742916 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* pd: Add pd_capable() to check PD capability of partner portShawn Nematbakhsh2017-11-071-0/+7
| | | | | | | | | | | | | | | | | | | It's undesirable to do BC1.2 detection on power swap, so add a function to check if the partner port is known to be PD-capable. BUG=chromium:780905 BRANCH=gru TEST=With subsequent CL, attach USB-PD phone capable of role swap. Verify USB 2.0 device is enumerated on plug, and not re-enumerated through a series of "pd # swap power" commands on the EC console. Also verify BC1.2 charging and PD charging are still functional on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ifa75c94e9758d3e407492bbda6fc52ed7bc378fa Reviewed-on: https://chromium-review.googlesource.com/755877 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* bd9995x: Use fixed PD-port-to-VBUS/VCC mappingShawn Nematbakhsh2017-11-071-7/+0
| | | | | | | | | | | | | | | | | The bd9995x driver was written to allow any PD port # to be VBUS or VCC, but the mapping is broken in a few places. Since all boards use VBUS = port 0, remove the conversion entirely. BUG=chromium:781849 BRANCH=kevin TEST=Verify PD and BC1.2 charging still works on kevin. Change-Id: I3687866835d1684342d9f746d91b3a6079ab5cc4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/755000 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Fizz: Modify thermal tableRyan Zhang2017-11-061-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify thermal table for Fizz reference patches: 627542, 288256, 329359 on off RPM step0 0 step1 16 2 2800 step2 27 18 3200 step3 35 29 3400 step4 43 37 4200 step5 54 45 4800 step6 64 56 5200 step7 97 83 5600 Prochot degree: active when t >= 88C release when t <= 85C Shutdown degree: when t >= 90C BUG=b:67487721, b:64439568 BRANCH=master TEST=fan target speed follows table, make -j buildall pass Change-Id: I3378668a560b8ddc568fe9cbf2703613fad8e4b6 Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/729606 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* charge_manager: Enter safe mode at bootShawn Nematbakhsh2017-11-022-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Charge port / current selection often needs to be significantly altered when a battery cannot provide sufficient charge, so have charge_manager initially enter safe mode. After a battery with sufficient capacity has been identified, charge manager will leave safe mode, and port / current selection will return to standard rules. BUG=chromium:777596 BRANCH=None TEST=Pass charge_manager unit tests. On kevin, remove battery, attach Apple PD charger, verify safe mode is not exited and device does not brown out. Hot-plug battery and verify safe mode is exited. Next, remove battery, attach to Samus, verify safe mode is not exited and device doesn't brown out. Hot-plug battery, verify that safe mode is exited and no active charge port, due to dual-role exclusion. Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733954 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chg_ramp: Add charge_is_consuming_full_input_current().Aseda Aboagye2017-11-012-7/+10
| | | | | | | | | | | | | | | | | | | Most boards had an identical implementation for this function, previously known as board_is_consuming_full_charge(). To reduce copy paste, let's just move it to common code. Boards that charge ramp without a battery will have to define their own implementation, but there probably won't be any boards like that in the near future. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ic99a378ac26dfd35d7d718bf9376eacfa8609166 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/748919 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: add IT5205 mux driverDino Li2017-10-312-0/+4
| | | | | | | | | | | | | | | | Add support the ITE IT5205 Type-C USB alternate mode mux. BRANCH=none BUG=none TEST=1. Successfully verify chip ID. 2. Verify set_mux() and get_mux() functions set and return consistent values. 3. The mux control register setting as expected after set_mux(). Change-Id: I9ff066dc9e74683df1371b70290e2aeaa86cb96b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/741211 Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Get rid of power_board_handle_host_sleep_eventFurquan Shaikh2017-10-311-8/+0
| | | | | | | | | | | | | | | | | power_board_handle_host_sleep_event was added to allow boards like poppy to enable/disable PMIC VR decay only once during S0ix entry/exit. Now that the chipset hooks have been fixed, there is no need of this board specific callback. If in the future, there is a need to have such a callback, this change can be reverted. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745982 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* port80: Clean up macrosFurquan Shaikh2017-10-311-0/+3
| | | | | | | | | | | | | | | | | 1. Add a new config option to define history buffer length. This allows boards to override this option if required. 2. Get rid of unused PORT80_POLL_PERIOD macro BUG=None BRANCH=None TEST=Verified that all port80 messages from a boot-up or S3 resume are present in port80 history buffer. Change-Id: Ie64680459f58358713a1b1445a0b99fcfe1c1cdc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745902 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Add default sleep event state HOST_SLEEP_EVENT_DEFAULT_RESETFurquan Shaikh2017-10-311-1/+9
| | | | | | | | | | | | | | | | | | Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to reinitialize S0ix flag, add a new default state HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of the code to take correct action depending upon the state that is currently triggered. BUG=None BRANCH=None TEST=Verified that SLP_S0# interrupt doesn't get asserted during runtime S0ix. Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745901 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-0/+6
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* twinkie: clean-up disabled SNIFFER_HEADER_V2 codeVincent Palatin2017-10-311-8/+0
| | | | | | | | | | | | | | | | | Remove all the CONFIG_USBC_SNIFFER_HEADER_V2 code, it was not fully satisfactory and we have a better alternative. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=make BOARD=twinkie Change-Id: I26d3396b2933be5276f916e3ac60c96347cb67f6 Reviewed-on: https://chromium-review.googlesource.com/743015 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ccd: pass 'ccd password' execution through tpm task contextVadim Bendebury2017-10-271-0/+1
| | | | | | | | | | | | | | | | | | It is necessary to be able to set password both from the Cr50 console and through a vendor command. This patch moves all password management logic to the TPM task context using the alternative vendor command path. BRANCH=cr50 BUG=b:62537474 TEST=verified that using Cr50 console CCD password still can be set and cleared as before. Change-Id: I0574caf931e3717567fdb270e406643eac47764b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/740914 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/npcx: Add support for pad-switching UARTNicolas Boichat2017-10-252-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NPCX5* only has one UART controller, which can be switched between 2 pads. We keep the default pad for EC console, however, we allow switching to the alternate pad for short, infrequent, transactions. Both pads are assumed to use the same baudrate and other line settings. When switching pad, we first configure the new pad, then switch off the old one, to avoid having no pad selected at a given time, see b/65526215#c26. Because of the added complexity of npcx_gpio2uart (and the fact that it uses the global variable "pad" define in uart.c), we move the implementation to uart.c (npcx_uart2gpio is also moved for consistency). When the pad is switched to alternate pad, characters input and output on the EC console (default pad) would be lost. To compensate for this, we: - Switch back to main pad in case of EC panic, so that output is shown on EC console. - Immediately abort current alternate pad transaction if a character is received on the default pad. Note, however, that the first character will be lost (this can be worked around by telling user to press enter, and have servod/FAFT always send 2 blank lines (instead of just one) before sending a command). - Inhibit pad switching for 500ms after receiving a character on default pad. Assuming a reasonable typing speed, this should allow developers to type console commands relatively comfortably, while not starving the alternate pad communication for too long. The logic above could be simplified significantly by implementing software flow control (XON/XOFF, see b/67026316). BRANCH=none BUG=b:65526215 TEST=While follow-up CL that writes long 1k buffers, the following works fine: - type 'uart' in EC console - Read battery power consumption from servod, which "types" in the EC console: while true; do dut-control ppvar_vbat_mw; sleep 1; done no failure is seen. TEST=Add this test code in uart_alt_pad_read_write, after the pad has been switched, and check that panic information is consistently printed correctly: { static int t; if (t++ > 20) t = t / ret; } Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/659458 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* PD: Make current USB PD Stack REV 3 compliantSam Hurst2017-10-242-11/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the following required features in the USB PD Rev. 3.0 specification. Not_supported control message: Inform a port partner that a particular message is not supported. Battery capabilities extended message: Report battery design capacity and last full charge capacity. Battery status data message: Report battery state of charge Collision avoidance: New scheme to avoid collisions caused when both source and sink want to send messages. Cable communication: Only the VCONN source can communicate with the cable plug. This is NOT implemented because although the drivers have the capability of communicating with a cable plug, the PD stack doesn't currently need to talk to a cable plug. This is okay since the current PD design doesn't source or sink more than 3 amps and all Type-C cables are required to be 3 amp capable. BUG=b:64411727 BRANCH=None TEST=`make -j buildall` Passed relevant PD Rev 2.0 compliance tests Successful PD negotiation with PD Rev 2.0 and 3.0 chargers Tested with low power none PD charger. Modified a Kevin to operate as a PD 3.0 charger and sent all required messages and verified the return messages. Also tested collision avoidance by verifying that a sink only transmits when the source indicates it's okay. Used Twinkie to verify that PD was operating as v3.0. Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: Ifd77e92ec4e9106236f9221393d2bfb97263d979 Reviewed-on: https://chromium-review.googlesource.com/603003 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tpm: let the caller of TPM reset decide if the EC needs to be reset tooVadim Bendebury2017-10-241-2/+2
| | | | | | | | | | | | | | | | | | | TPM reset sequence when TPM wipeout is requested has a side effect of rebooting the entire device. This is not always desirable, in some cases other actions need to happen before the device is rebooted. This patch makes resetting the EC the TPM reset caller's responsibility, BRANCH=cr50 BUG=none TEST=verified that RMA reset and WP disable properly wipe out the TPM and reboot the device. Change-Id: I6e827ce923a2454ae5b2e2597d1a4c9390bbb8b6 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733813 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* rma: process proper auth codeVadim Bendebury2017-10-241-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When RMA process has been initialized and the user entered the expected authentication code value, the Cr50 needs to wipe out TPM memory, open and unlock CCD and reboot the device. This patch adds a function to accomplish that. User response is validated on the TPM task context, and TPM reset request also requires TPM task processing. To decouple response processing from the following reset, the response processing is handled by a hook task callback, delayed for 1s to make sure that user receives the response. After TPM has successfully reset the CCD is reinitialized with RMA 'opened' and the device is rebooted. Just in case something goes wrong with the unlock and the hook is not invoked, add a 10s deferred function to take the EC out of reset so that the device still can reboot. BRANCH=none BUG=b:67007905 TEST=on a Bob device: - on the Cr50 console enter 'ccd lock', verify that ccd is locked (by examining output of the 'ccd' command) - at the bash prompt enter gsctool -r -s -t, copy the authentication code from the Cr50 console and pass it to gsctool. - observe the device reset TPM wiping out its memory, enable CCD and reboot. Change-Id: I6fafb5e642cb2b6f2040507a7f1989607fd31316 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/729983 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* host_event: Perform lpc_init_mask before keyboard/button initFurquan Shaikh2017-10-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | keyboard/button init are responsible for checking if user requested manual recovery. However, by this time, hook init is not run and hence host event set operation for manual recovery is dropped. This change adds a call to lpc_init_mask before keyboard/button init operations are performed. BUG=b:68189465 BRANCH=None TEST=Verified that manual recovery works fine. Recovery using software command works too: reboot ap-off hostevent set 0x4000 powerb Change-Id: I15cb648d4b253a523293c7ab2cd3e8e08e31a763 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/735799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: ppc: Add support for TI SN5S330.Aseda Aboagye2017-10-231-0/+4
| | | | | | | | | | | | | | | | | | | | This commit adds a basic driver for the TI SN5S330. This driver just sets up the IC and provides an API to turn on or off the PP2 FET. BUG=b:67663166, b:67663124 BRANCH=None TEST=Enable code for zoombini; Flash a board which has the SN5S330 stuffed; Verify that we're able to perform PD negotiation and negotiate all the way up to 20V. TEST=Boot only on AC. sysjump to RW, verify that board does not brownout. Change-Id: I9c147ee8465eed878843cf902db301d62e8f627e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/722104 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add task-safe API to control 5V rail.Aseda Aboagye2017-10-232-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For certain cannonlake designs, the 5V rail can be controlled by both the chipset task as well as other tasks such as the USB charger tasks to perform BC1.2 detection. This commit introduces an API that allows the tasks to enable/disable the 5V rail. Enable requests will immediately enable the rail, however, attempting to disable the rail will only result in a request. Once all tasks want to turn off the 5V rail, the rail will be turned off. A bitmask is introduced to keep track of the requests. Index 0 is for the chipset task. All of this is gated behind a config option: CONFIG_POWER_PP5000_CONTROL BUG=b:65991615 BRANCH=None TEST=With other zoombini code, verify that 5V can be enabled and disabled. Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/722322 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* isl9238: Add support for providing power using OTGNicolas Boichat2017-10-201-2/+18
| | | | | | | | | | | BRANCH=none BUG=b:66575472 TEST=Flash lux and wand, wand can provide power to lux. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I59091c509b78bacf9f382550ab380a77fbf68ba9 Reviewed-on: https://chromium-review.googlesource.com/725122 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: pd: Make PDO find / extract functions non-staticShawn Nematbakhsh2017-10-191-4/+23
| | | | | | | | | | | | | | | | Allow other modules to call pd_find_pdo_index() / pd_extract_pdo_power() in order to get information about current PDOs. BUG=chromium:775542 TEST=Manual on kevin, verify 20V negotiation with zinger still works. BRANCH=servo Change-Id: I1861a0226501bda13e7d576d0971d841da9d2b74 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/724682 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_ramp: Ramp USB-C DTS sourcesShawn Nematbakhsh2017-10-192-1/+7
| | | | | | | | | | | | | | | | | | | | suzy-qable advertises 1.5A, but its actual capability depends on the host USB port it is attached to. Since suzy-qable is ubiquitous and other DTS sources may behave in the same way, ramp the input current limit in order to find a reasonable maximum. BUG=chromium:770296 BRANCH=None TEST=Attach suzy-qable to kevin and reef, verify that neither OCs and EC console via cr50 is available on reef. Also verify donette chargers kevin at 3A and does not ramp. Change-Id: Idd0683ede3a44111a01da6b4faab52f388ee82fd Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693295 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Remove ACCESSORY statesShawn Nematbakhsh2017-10-193-37/+11
| | | | | | | | | | | | | | | | | | | According to the USB-C spec, when a debug accessory is identified, we may optionally establish USB PD communication over CC. Some DTS partners (eg. servo_v4) expect us to speak PD, so let's make it so. There is no need for special ACCESSORY states, these do not exist in the PD spec. BRANCH=servo BUG=chromium:737755,b:65837068 TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify EC and cr50 consoles are available through servo_v4. Change-Id: I59d1ca50b4766509eccf38562cdf926578138585 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693294 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Add "freeze" dual-role policyShawn Nematbakhsh2017-10-193-0/+10
| | | | | | | | | | | | | | | | | Add a new DRP policy to "freeze" the power role of each port, never toggling automatically, though manual role swaps may still occur. BUG=chromium:769895 BRANCH=servo TEST=On servo_v4, verify DUT port stays in SRC role and POWER port stays in SNK role while disconnected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ibff3cd1ffaf0e884b030c231003763a57acbe02e Reviewed-on: https://chromium-review.googlesource.com/715276 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* host_event_commands: Add support for always reporting masksFurquan Shaikh2017-10-182-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new mask type (ALWAYS_REPORT mask) that is set by default to certain host events that should always be reported to the host irrespective of the state of SCI, SMI and wake masks. This mask includes host events like critical events resulting in shutdown or reboot, events that are consumed by BIOS, etc. Now that ALWAYS_REPORT mask is added, this change also updates the way EC manages set/query operations for host events: 1. During set operation, EC will check if the host event is present in any of the 4 masks - SCI, SMI, wake and always report. If yes, then it is set in hostevents. 2. During query operation, EC will extract the lowest set event from hostevents, clear it and return it back to the host. In order to reflect the above change in EC behavior, a new feature bit is used EC_FEATURE_UNIFIED_WAKE_MASKS. This allows the host to decide when wake mask needs to be set before checking for host events. BUG=None BRANCH=None TEST=make -j buildall. Also verified following: 1. Wake from S3 works as expected. Host is able to log correct wake sources (Verified power button, lid open, base key press and tablet mode change on soraka). 2. Wake from S5 works as expected. Host is able to log correct wake sources (Verified power button, lid open on soraka). 3. Wake from S0ix works as expected (Verified power button, lid open on soraka). 4. Software method to trigger recovery still works fine: reboot ap-off hostevent set 0x4000 powerb Change-Id: I62e5c1f82247c82348cd019e082883d86ec2688f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/719578 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Add CONFIG_IGNORE_G_UPDATE_CHECKSMarius Schilder2017-10-181-0/+5
| | | | | | | | | | | | | | | | In some scenarios we want to take RW updates w/o taking version numbers into consideration, much like the behavior we get w/ CR50_DEV. But then without the additional CR50_DEV features enabled for the rest of the code. BRANCH=none BUG=none TEST=compiles Change-Id: I7dd946ab77bbdc35850ed934cd53735418e13845 Reviewed-on: https://chromium-review.googlesource.com/724967 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Trybot-Ready: Marius Schilder <mschilder@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-5/+22
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* EFS: Sysjump to active copyDaisuke Nojiri2017-10-171-1/+1
| | | | | | | | | | | | | In EFS, EC needs to sysjump to the active copy, which is hashed and validated by the AP. BUG=b:67748602 BRANCH=none TEST=Verify Depthcharge makes EC jump to RW. Change-Id: I2ca893f7691ad776a791f2044dd7a0983d06e3c5 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/717676
* charge_manager: Support no-battery / no-host boardsShawn Nematbakhsh2017-10-171-0/+4
| | | | | | | | | | | | | | | | Boards without batteries and/or without host command support may wish to use charge_manager. BUG=chromium:769895 BRANCH=None TEST=`make buildall -j` Change-Id: I2455528de3300a0651791752a05409c888b5f2a3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/713943 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* [fan] Add CONFIG_FAN_SPEED option to override EC fan speedChris Ching2017-10-131-0/+3
| | | | | | | | | | | | | | | | Fans will be initialed at the given RPM, and not the max speed. Changed kahlee to use new method and set speed to ~50%, down from 75% BUG=b:67055475 TEST=run on kahlee board BRANCH=none Change-Id: Iad40a58b531f46ac80572b47aef9378b47222be1 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://chromium-review.googlesource.com/714386 Commit-Ready: Chris Ching <chingcodes@chromium.org> Tested-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
* cleanup: Use CONFIG_BATTERY to indicate whether a board has a batteryShawn Nematbakhsh2017-10-131-1/+13
| | | | | | | | | | | | | BUG=b:35528297 BRANCH=None TEST=`make buildall -j` Change-Id: I9e4814b4172f20711f7edd691c9569f9130aec8e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/713395 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: add alternative TPM command execution contextVadim Bendebury2017-10-131-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | The TPM task provides access to various cryptographic functions which require huge stack size. Some other contexts might require to execute these functions, but no other task in the system has enough stack. The suggested solution is to create an alternative TPM task execution path, where the command comes not from the communications interface (SPI or I2C), but from another task in the system. An interface function is created to allow a single task to pass the command to the TPM task. The task requesting the alternative execution path creates the command context, sends an event to the TPM task to alert it to the presence of the command and then polls the flag indicating that the TPM task has completed execution of the command. BRANCH=cr50 BUG=b:67008109 TEST=tested after applying the next patch (add console command for generating RMA auth challenge). Change-Id: I168489a5fbb4a3e1d718198812019116738b2f61 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/699523
* motion_sense: Add CONFIG_DYNAMIC_MOTION_SENSOR_COUNT config optionScott Collyer2017-10-112-0/+6
| | | | | | | | | | | | | | | | | | | | | Some projects, such as Coral use a common image to support different SKUs. In this case the number of motion sensors supported may need to be determined at runtime. CONFIG_DYNAMIC_MOTION_SENSOR_COUNT removes the const assumption for the global variable motion_sensor_count. Based on CL https://chromium-review.googlesource.com/444587 BUG=b:38271876 BRANCH=None TEST=make -j buildall Change-Id: I4dd3384d245641136f3329b60d1d941927366387 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/711194 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* chip/stm32/clock: Optionally use LSE as RTCCLKPhilip Chen2017-10-111-0/+3
| | | | | | | | | | | | | | | | | | | | The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz. To use stm32 RTC for applications requiring accurate timing, let's setup LSE (a more accurate clock source) as RTCCLK. Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally. BUG=b:63908519 BRANCH=none TEST=boot scarlet rev1 and wait for an hour, confirm rtc time == kernel system time. Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/679601 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: rename usb_updater into gsctoolVadim Bendebury2017-10-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb_updater utility has long been not just an updater, and has long been using other interfaces in addition to USB. gsctool is a much more suitable name. CQ-DEPEND=CL:709776 BRANCH=cr50 BUG=b:67007500 TEST=verified that make -C ./extra/usb_updater generates ./extra/usb_updater/gsctool: $ ./extra/usb_updater/gsctool --help Usage: gsctool [options] <binary image> This updates the Cr50 RW firmware over USB. The required argument is the full RO+RW image. Options: [...] $ Change-Id: I3ab70c28acf3664ddefaa923a87ba1fd5c3c437b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/709738 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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