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* npcx: Define CONFIG_DATA_RAM_SIZEDaisuke Nojiri2017-08-071-1/+16
| | | | | | | | | | | | | | | | | | This patch defines CONFIG_DATA_RAM_SIZE, which indicates the size of the RAM used for data, thus can be marked as non-executable. If it's not defined, it defaults to CONFIG_RAM_SIZE. Thus, other chips are not affected. BUG=b:36037354 BRANCH=none TEST=buildall. Run 'sysjump disable' on Reef and verify mpu_protect_ram is successful. Change-Id: I54d74fd1dabff7e1013fff2542fd02c3646803d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/596518 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fix compilation with coreboot-sdkStefan Reinauer2017-08-041-0/+7
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=none TEST=The following sequence passes sudo emerge coreboot-sdk export CROSS_COMPILE_arm=/opt/coreboot-sdk/bin/arm-eabi- export CROSS_COMPILE_i386=/opt/coreboot-sdk/bin/i386-elf- export CROSS_COMPILE_nds=/opt/coreboot-sdk/bin/nds32le-elf- make buildall -j Change-Id: I4cafbcd70efd6bdf102f848f1cca4772b4ccd10e Reviewed-on: https://chromium-review.googlesource.com/595207 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* PD_CONTROL: add subcommand to power up a TCPC.Caveh Jalali2017-08-032-1/+10
| | | | | | | | | | | | | | | | | | | add a subcommand to the PD_CONTROL message to power up a specific TCPC. in practice, this typically just takes the TCPC out of sleep mode for cases where sleep mode is controlled by the EC. under the covers, board_set_tcpc_power_mode() gets a weak function definition so we don't need to special case this everywhere. TEST="make buildall" passes; "make tests" passes for reef. BRANCH=none BUG=b:35586895 Change-Id: Ib50e265d11eca10c3714049d8cfdf2657eff48c1 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/596796 Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_update: Add a way to fetch touchpad informationNicolas Boichat2017-08-032-0/+20
| | | | | | | | | | | | | | | | | | | | | We'd like to know touchpad vendor/product id, as well as currently running FW version. This CL does that by adding a new UPDATE_EXTRA_CMD_TOUCHPAD_INFO command. We also make the interface more generic by adding a CONFIG_TOUCHPAD configuration option, even though we only support Elan touchpads currently. BRANCH=none BUG=b:63418037 TEST=Flash hammer, ./usb_updater -t Change-Id: Icce3c785eb3235bcc50b2ae7c0227ce11cbc9f2b Signed-off-by: Nicolas Boichat <drinkcat@google.com> Reviewed-on: https://chromium-review.googlesource.com/593000 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* pd_log: Make PD logging more generic for general purpose loggingShawn Nematbakhsh2017-08-023-3/+42
| | | | | | | | | | | | | | | | | | We can re-use our pd_log FIFO for other purposes, such as TPM logging. Carve out event_log, a generic logging module which pd_log is compatible with. BUG=b:63760920 TEST=On kevin, verify PD logging is still functional and entries are seen in dmesg. BRANCH=None Change-Id: I8e6ad6f93e9eebc676aca64652c60f81da471a94 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/597314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_*: Fix __packed struct coding styleNicolas Boichat2017-08-021-4/+4
| | | | | | | | | | | | | | | | EC code style should use __packed at the end of the structure, rather than __attribute__((__packed__)). BRANCH=none BUG=none TEST=Flash hammer Change-Id: Ib5dc71a8439038d46b9bc331bdabff7c57c7300a Signed-off-by: Nicolas Boichat <drinkcat@google.com> Reviewed-on: https://chromium-review.googlesource.com/597037 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: CCD V1 controls UART accessRandall Spangler2017-08-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP and EC UART now use the CCD V1 capabilities to determine when access is allowed. Transmit to AP and EC can be toggled independently from read access to output from those UARTs. Note that disabling read access disables both transmit and receive. That is, it's not possible to set a UART where transmit is allowed but receive isn't. Why would you want to do that, anyway? See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 ccdoops ccdset cr50fullconsole always -> so we can use ccd command for testing ccd -> AP RX+TX, EC RX+TX ccdset uartecrx unlesslocked ccdset uartectx ifopened ccdset uartaprx always ccdset uartaptx unlesslocked ccdunlock ccd -> AP RX+TX, EC RX ccdlock ccd -> AP RX, EC disabled ccdoops ccdset cr50fullconsole always ccd -> AP RX+TX, EC RX+TX ccdset uartaprx ifopened ccdlock ccd -> AP disabled, EC RX Change-Id: I55db5897bb52cd60658ab221eadf5c59fc86744a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/595196 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_i2c: Fail if board I2C bridge is disabledRandall Spangler2017-07-312-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add usb_i2c_board_is_enabled(). On Cr50, this is now also connected to the I2C CCD capability. The USB-I2C bridge can only be used when the capability is available. On other platforms (Servo V4, etc.) where usb_i2c_board_enable() is a no-op, add a dummy implementation which always returns true. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 Connect host PC to dev board USB port On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x8001 ccdoops --> reset I2C config ccd i2c disable --> I2C disabled On host PC: sudo servod -c ccd_cr50.xml -c reef_r1_inas.xml dut-control pp3300_ec_shv_reg --> fail, error 0x0006 ccd i2c enable --> I2C enabled ccdunlock --> I2C disabled ccdoops --> I2C enabled ccdset i2c unlesslocked ccdlock --> I2C disabled ccdunlock --> I2C enabled Change-Id: Ia3df32e239a5f7c5915bc6c7e408ce0dc8b26c89 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590577 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* driver: Move PI3USB9281 to bc12 directory.Aseda Aboagye2017-07-311-6/+4
| | | | | | | | | | | | | | | | | | | | The primary purpose of the Pericom PI3USB9281 is for BC1.2 detection. Therefore, move the driver to the bc12/ directory. Additonally, rename the config option to match. CONFIG_USB_SWITCH_PI3USB9281 => CONFIG_BC12_DETECT_PI3USB9281 BUG=None BRANCH=None TEST=`make -j buildall` Change-Id: I02f17064c0625e62d6779f895e69899c24898f74 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/594710 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: Add support for TI BQ24392.Aseda Aboagye2017-07-311-0/+3
| | | | | | | | | | | | | | | | | | | | | | The BQ24932 is a dual single-pole single-throw USB 2.0 high-speed isolation switch with charger detection capabilities. The device's charger detection circuitry can support USB Battery Charging Specification version 1.2 (BC1.2), Apple, TomTom, and other non-standard chargers. BUG=None BRANCH=None TEST=`make -j buildall` TEST=Enable support for the BQ24392 on a board. Verify that it complies. Change-Id: I82f426f1eedabdbb6b951a6ce0252135de3368db Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/592133 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/usb_hid_touchpad: Widen pressure field to 10 bitsNicolas Boichat2017-07-311-4/+4
| | | | | | | | | | | | | | | | | | | | id only really needs 4 bits (16 touch events should be more than enough), so we can steal 2 bits from that field. We also reorder the fields to make sure that width/x are aligned on 8-bit boundary. BRANCH=none BUG=b:63936194 TEST=Flash hammer, touchpad works, ABS_PRESSURE > 255 is reported when a palm is pressed on the touchpad. Change-Id: I1abf1bf53cc9dd998082cea5dc7cd3be17f99ec6 Reviewed-on: https://chromium-review.googlesource.com/583297 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: KT Liao <kt.liao@emc.com.tw>
* cr50: provide chip factory mode supportVadim Bendebury2017-07-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | When in factory mode, we should not be trying to figure out board strapping options, just enable SPI interface so that the tester can communicate with the chip. Also, to close the loop with the tester, let's add indication of the cert installation result, by setting the two top bits of the DUMMY (aka underrun) character to 1 and the lower bits to the endorsement operation result (0 means success, nonzero values communicate different failure modes) and by preventing the TPM driver from sending anything but underrun chars on the SPI interface. BRANCH=cr50 BUG=b:63686091 TEST=pending Change-Id: I1a22ed6988ad87dd929a393359c4604e6ecd3b58 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/578651 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Add OTP supportGwendal Grignou2017-07-285-6/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One Time Programmable memory can be used to store permanent data like serial numbers. Reorganize the code to support writing serial number to OTP, in addition to pstate (if using its own memory bank) or autogenerate from unique id (hammer). + Add CONFIG_OTP to enable OTP code + Add CONFIG_SERIALNO_LEN to indicate the size of the serial number string. Currently set to 28, when USB serial number is needed. + Expose flash_read|write_pstate_serial and add otp_read|write_serail, remove more generic flash_read|write_serial. + Make board_read|write_serial generic, declared outside of USB subsystem. Priority order to read|write serial string: - board definition (like hammer) - pstate location, if stored in its private memory bank - otp area If none of these methods are available, a compilation error is raised. BUG=chromium:746471 BRANCH=none TEST=compile Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/580289 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* power: Allow host to request higher-power wakeable S3Shawn Nematbakhsh2017-07-281-1/+3
| | | | | | | | | | | | | | | | | | | | Allow host to request a higher-power S3 variant, "wakeable S3", in which more wakeup sources will be enabled by the EC. The actual implementation and list of wake sources is left up to the chipset power driver and/or board code. BUG=b:63037490 BRANCH=gru TEST=With subsequent commit, compile on scarlet w/ power sequencing version = 2. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I469f0cd969052f173cb176196bb6d05f6f76fdb5 Reviewed-on: https://chromium-review.googlesource.com/572210 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* cr50: Disable CCD on board ID mismatchRandall Spangler2017-07-272-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is a board ID mismatch and rollback is not possible Cr50 firmware will enter a limited mode which only support Cr50 firmware upgrade. All other features must be disabled, because it is not possible to know which features should be allowed on the mismatched board. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build, define CONFIG_CMD_CCDDISABLE ccdinfo --> state=opened ccddisable --> state=locked(disabled), all capabilities disabled ccdunlock --> access denied ccdopen --> access denied ccdreset --> access denied ccdpassword --> access denied ccdset --> access denied ccdoops ccdinfo --> state=opened, back to defaults Change-Id: Idb66fb1f3d5106aa0c2cb6addf2404ea9942b0d6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/590070 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Preserve CCD state across deep sleepRandall Spangler2017-07-271-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two bits in a long-life register to hold the current CCD state across deep sleep. Update the bits on CCD config change, and restore them on init. This is necessary because Cr50 loses RAM contents on deep sleep. It would be really inconvenient to open CCD, get a cup of coffee, and come back to find CCD has locked again because Cr50 was idle too long. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=cr50 TEST=manual with CR50_DEV=1 build ccdinfo --> state=opened idle d ccdunlock ccdinfo --> state=unlocked (wait for deep sleep) sysinfo --> reset flags = hibernate wake-pin ccdinfo --> state=unlocked reboot sysinfo --> reset flags = hard ccdinfo --> state=opened Change-Id: I7864f374af5c159bc9691b094958fb030f3cb8ad Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575996 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* battery/max17055: Add max17055 fuel gauge driverPhilip Chen2017-07-271-0/+1
| | | | | | | | | | | | | | | | | BUG=chromium:736603 BRANCH=none TEST=Follow the steps below 1) add MAX17055 config to Scarlet and build the code 2) hook up max17055 eval board and a single cell battery 3) battery command from ec console shows reasonable numbers for temperature, voltage, and charge percentage Change-Id: I3f838ff92c591665e9f1d0a7ba636ff83d9b7612 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/578300 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash: add flash selection supportWei-Ning Huang2017-07-273-0/+29
| | | | | | | | | | | | | | | | | | | | | | | Some chips require special operations before flash can be accessed (read, write, erase), without it the flash operations could be corrupted. The chip that requires this should enable the CONFIG_FLASH_SELECT_REQUIRED config, which exposes EC_FLASH_INFO_SELECT_REQUIRED in flashinfo flags. Before any flash operations is executed on the chip, EC_CMD_FLASH_SELECT should be issued to notify the chip to prepare for the flash operations. BRANCH=none BUG=b:63685022 TEST=with depended CLs, touchpad interrupt should be disabled when flashrom is in progress. CQ-DEPEND=CL:*416548 Change-Id: I96455adbe739d5f924edf382a2752404a7c5ad04 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/582374 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* button: Add recovery button to mkbp button stateFurquan Shaikh2017-07-211-0/+1
| | | | | | | | | | | | | | Pass in recovery button press/release information to AP using MKBP button driver. BUG=b:63893483 BRANCH=None TEST=Behavior verified by Shelley. Change-Id: I7a6e50ec8595d99327b5fc8e822bf762e0ce13e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/580539 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: modify tpm_endorse() error reporting logicstabilize-9765.7.BVadim Bendebury2017-07-201-1/+17
| | | | | | | | | | | | | | | | | | Using zero to represent success make it cleaner when processing return values of this function. Also, let's report different failures using different error values. Note that nobody checks this function's return value yet. BRANCH=cr50 BUG=b:63686091 TEST=none Change-Id: If25d30e637701f6c37f3ce75e5a5d5315e0e86e9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579583 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-07-204-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CNL: Don't build CNL in tests w/o chipset tasks.Aseda Aboagye2017-07-201-0/+1
| | | | | | | | | | | | | | | | | | | When compiling target tests for a board that defines CONFIG_CHIPSET_CANNONLAKE, the build would fail due to the chipset code being built without a chipset task. This commit removes the Cannonlake chipset code when building a test that does not have a chipset task (and use Cannonlake). BUG=None BRANCH=None TEST=make -j BOARD=zoombini tests; verify that build succeeds. Change-Id: I15a5729db64314a8d6566be879f7c356ffa95725 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/578316 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Add physical presence state machineRandall Spangler2017-07-194-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used as part of case closed debugging configuration. Currently, this only adds the state machine, and a test command which is available when CR50_DEV=1. It also adds a new sleep mask flag for physical presence detect, instead of oveloading FORCE_NO_DSLEEP. The physical presence state machine supports both short (tap 5 times in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes apart) sequences. It will call a callback function at the end of the sequence, so that multiple things can each request physical presence in turn. This will be used by ccdopen / ccdunlock / testlab commands for CCD V1. Eventually, CCD config will replace the unlock sequence handling in wp.c. But for now, we don't touch that. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual Short sequence: pp short pp pp pp # See "Physical presence good" Timeout pp short pp # 15 sec later, get timeout error Long sequence: pp long pp pp pp (wait 2 sec) pp (wait 2 sec) pp # See "PP good" Long sequence, presses too fast: pp long pp pp pp pp # See "PP L too soon" (wait 2 sec) pp (wait 2 sec) pp # See "Physical presence good" Abort: pp short pp abort # See "Physical presence aborted" Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568796 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ec_commands: Fix more portability issuesShawn Nematbakhsh2017-07-181-1/+1
| | | | | | | | | | | | | | BUG=chromium:741711 BRANCH=None TEST=`make buildall -j`, also verify kevin kernel builds with new copy of ec_commands.h. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia7fab98d61ecac727a0007d6f59ab4c9047de049 Reviewed-on: https://chromium-review.googlesource.com/576231 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ec_commands: Add define for maximum number of PD portsShawn Nematbakhsh2017-07-181-0/+3
| | | | | | | | | | | | | | | | It's helpful for the host to know the maximum number of PD ports that can possibly exist in a cros-ec device. BUG=chromium:741711 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic8a9eb22dc0bf51c8f5e1dfe380ca8f187481070 Reviewed-on: https://chromium-review.googlesource.com/576138 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* hammer: Enable Link-Time-Optimization CONFIG_LTONicolas Boichat2017-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | We need to add __keep to the USB descriptors, otherwise they get thrown away. Also, for some reason the optimized RWSIG task uses a little bit more stack space, so account for that: 1 RWSIG 00000000 0.264350 1096/2048 BRANCH=none BUG=b:63610290 TEST=make BOARD=hammer -j make newsizes build/hammer/RO/ec.RO.flat shrank by 2052 bytes: (37336 to 35284) build/hammer/RW/ec.RW.flat shrank by 3172 bytes: (50508 to 47336) Flash hammer, touchpad, keyboard, update all still work fine. Change-Id: I39ffd320dae883596ce481efc4adec6e3c23000b Reviewed-on: https://chromium-review.googlesource.com/567909 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Jump to RW earlyDaisuke Nojiri2017-07-141-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes EC run vboot in the HOOK task. The vboot routine requires battery and charger info. It waits in a deferred call loop until the charge manager is initialized. BUG=b:63586051 BRANCH=none TEST=Verify the following cases: A. Hardware reboot (type-c/BJ) 1. Unplug AC in S0 then plug in AC: BOOT/BOOT 2. Unplug AC in S5 then plug in AC: S5/S5 3. Unplug AC after A.2 then plug in AC: S5/S5 4. Press PB in S5: BOOT/BOOT B. Software reboot (type-c/BJ) 1. Run EC reboot command in S0: BOOT/BOOT 2. Run EC reboot command in S5: BOOT/BOOT 3. Run EC reboot ap-off command in S0: S5/S5 4. Run EC reboot ap-off command in S5: S5/S5 5. Run host reboot command: BOOT/BOOT 6. Run host shutdown command: S5/S5 C. Recovery tests 1. Press RB and PB in S0: FAIL(*1)/PASS 2. Press RB and PB in S5: FAIL(*1)/PASS(*2) 3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS 4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2) *1: b:63668669 *2: b:63669512. Requires one more PB press. Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568699 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Move common code under common/vbootDaisuke Nojiri2017-07-131-1/+45
| | | | | | | | | | | | | | | This patch moves the code which can be shared with other data verification schemes (e.g. RWSIG) under common/vboot. It also adds unit tests for it. BUG=b:38462249 BRANCH=none TEST=make run-vboot. Verify verification succeeds on Fizz. Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/563463 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Verify and jump to RW_A or RW_BDaisuke Nojiri2017-07-131-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gives EC the capability of verifying and jumping to RW_A or RW_B. EC tries the slot stored in a persistent storage (e.g. BBRAM). If verification fails due to invalid contents, EC tries the other slot. AP's expectation and its reaction to the state of the slots and the currently running image are summarized below. Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC won't try to verify or jump to RW yet. | AP expects X ----------+--------------------------- SLOT_A=X | proceed SLOT_B=X | proceed ----------+--------------------------- SLOT_A=X' | reboot to B SLOT_B=X | proceed ----------+--------------------------- SLOT_A=X | proceed SLOT_B=X' | reboot to A ----------+--------------------------- SLOT_A=X' | write X to B, reboot to B SLOT_B=X' | write X to A, reboot to A BUG=b:38462249 BRANCH=none TEST=Lock the system and boot Fizz on barrel-jack and type-c. Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/556286 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Build RW_B and support sysjump to itDaisuke Nojiri2017-07-131-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows a board to include another RW image in ec.bin. The size of each copy is a quarter of the flash size on Fizz. BUG=b:38462249 BRANCH=none CQ-DEPEND=CL:568297 TEST=Run sysjump RW/A/B. Verify there is no size change by running make savesizes/newsizes. Run objdump -h build/fizz/ec.obj: Idx Name Size VMA LMA File off Algn 0 .image.RO 0001700c 10088000 10088000 00008000 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .image.RO.key 00000340 1009f00c 100a7c40 0001f00c 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .image.RW 00016ddc 1009f34c 100c8000 0001f34c 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 3 .image.RW.sign 000001b8 100b6128 100e7c00 00036128 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .image.RW_B 00016ddc 100b62e0 100e8000 000362e0 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 5 .image.RW_B.sign 000001b8 100cd0bc 10107c00 0004d0bc 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .padding 00000001 100cd274 10107fff 0004d274 2**0 CONTENTS, ALLOC, LOAD, DATA 7 .ARM.attributes 00000014 00000000 00000000 0004d275 2**0 CONTENTS, READONLY Change-Id: Iaa687c1d7d704fec4cccfa127376c8db102267fa Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/557305 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* charger/rt946x: add Richtek rt946x charger driverPhilip Chen2017-07-131-0/+2
| | | | | | | | | | | | | | | | | BUG=chromium:736821 BRANCH=none TEST= 1) add RT9467 config to Scarlet and build the code 2) hook up rt9467 eval board with dummy load 3) verify the i2c traffic: set voltage, set current, and get device id Change-Id: Ie0dc2650711465b89eb4a5fbf69a326d6277b583 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/565055 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* board: Add initial support for zoombini.Aseda Aboagye2017-07-111-11/+4
| | | | | | | | | | | | | | | This commit adds the initial board support for zoombini. BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I38a108d607ed1a33a0e5b588d4d463026919ac20 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564800 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: tcpm: ps8xxx: Add support for PS8805.Aseda Aboagye2017-07-111-0/+1
| | | | | | | | | | | | | | | | | | | | | This commit adds support for the PS8805, another Parade Tech TCPC with integrated superspeed muxes. This also creates a generic Parade Tech TCPC driver which supports the PS8xxx series. The current supported TCPCs are: - PS8751 - PS8805 BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I78383af414996e0e8d6220985d286f95267136f8 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564799 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add Cannonlake chipset support.Aseda Aboagye2017-07-111-0/+1
| | | | | | | | | | | | | BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564798 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/flash: Add option to set PSTATE to be locked by defaultNicolas Boichat2017-07-081-0/+7
| | | | | | | | | | | | | | | | | For hammer, we do not want to require finalization in factory, so we just protect RO whenever WP GPIO is set. BRANCH=none BUG=b:63378217 TEST=Enable CONFIG_FLASH_PSTATE_LOCKED, flash hammer, check with flashinfo that RO protection matches WP status. Change-Id: I902ee478c00a3c932277d2a7d0622c070654a5eb Reviewed-on: https://chromium-review.googlesource.com/563217 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/pwm: Prevent sleeping while PWM output is activeNicolas Boichat2017-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | STM32F0 cannot keep PWM output active when chip is in deep sleep. The only other board that uses both CONFIG_LOW_POWER_IDLE and CONFIG_PWM on stm32 is jerry, and this logic should also apply to it. Also, switch using_pwm from array to bitmask to simplify handling. BRANCH=none BUG=b:36173380 TEST=On AP, tell it to autosuspend hammer: echo auto > /sys/bus/usb/devices/1-2/power/control Then see, using idlestats, that hammer does to deep sleep. In hammer console: pwm 0 50, see that PWM output is stable, idlestats shows EC does not sleep. In hammer console: pwm 0 -1, idlestats shows EC sleeps again. Change-Id: Ic74c1905364fe4335239da95a99193d0e3e979f7 Reviewed-on: https://chromium-review.googlesource.com/541115 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* core/cortex-m0/curve25519: Integrate fast curve25519 implementationNicolas Boichat2017-07-031-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move generic implementation to curve25519-generic.o - Always use optimized version on cortex-m0. - Rename .s files to .S, remove unnecessary lines in assembly files. - Rename crypto_scalarmult_curve25519 to x25519_scalar_mult to match the signature provided by the generic implementation. - Replace some handcoded memcpy with function calls - Remove unnecessary "volatile" specifications in the code. BRANCH=none BUG=b:62813194 TEST=To test old implementation only: - Increase CONFIG_RO_SIZE to 60kb - Increase console stack size to 2048 make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, taskinfo => Used to takes ~4'17" to run (X25519 duration 256347 us). 1496/2048 stack size usage in CONSOLE task => Now takes ~1'25" to run (X25519 duration 84520 us) 732/2048 stack size usage in CONSOLE task TEST=In test/x25519.c, uncomment #define TEST_X25519_1M_ITERATIONS make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, wait ~23 hours, test passes. TEST=- Define CONFIG_CURVE25519_CORTEXM0 (next patch) makes newsizes build/hammer/RW/ec.RW.flat shrank by 1888 bytes: (52208 to 50320) Change-Id: Icce38d3c32f431a85ac0f951cf34456b490dc665 Reviewed-on: https://chromium-review.googlesource.com/540962 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: Add RMA reset auth challenge-response cryptoRandall Spangler2017-06-302-0/+86
| | | | | | | | | | | | | | | | RMA auth uses X25519 to generate a relatively small challenge and response. Currently, nothing calls the rma_auth code. We'll need console and TPM vendor commands to do so. BUG=b:37952913 BRANCH=none TEST=make buildall Change-Id: Iec7f2d0e3dc8243f79b009ead16bb3ba9f1bef9d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544184
* usb_pd: only service interrupts on enabled ports.Caveh Jalali2017-06-301-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as it turns out, we're pretty aggressive in iterating over all TCPCs checking for alerts when any of them generate an interrupt or their interrupt line is low. this can cause unfortunate behavior if the driver hasn't initialized itself (and the chip) yet for interrupts to be handled or we've released (disconnected) the driver so we can do a TCPC firmware update. so, check the PD task state to see if it makes sense to service the port's interrupt. note: there seems to be a quirk with the ps8751 in that it holds its ALERT# (interrupt) line low during firmware update. this line is supposed to be falling edge triggered, so it's technically not interrupting, but since we also poll the line level, we think there's a continuous interrupt that isn't acutally there. we get away with this because pd_exchange_status() has a 5ms delay in its polling loop to avoid spinning. the particular test case was to unplug the PD power brick during TCPC firmware update (over i2c). the interrupt handler would be called, accessing the TCPC over i2c and causing all sorts of havoc. TEST=tested with follow-up CLs and verified ps8751 firmware update works on electro. BRANCH=none BUG=b:35586896 Change-Id: I880cff49e0e9637256efa9003bcc46274536e631 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/544661 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Add support for reporting device eventsDuncan Laurie2017-06-303-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to report specific wake events from differernt devices add a host command that allows setting device event mask, and triggering a host event when that device event is set. This is done as a separate command and mask because we are running out of host events, and it takes over the unused thermal overload event that was never used in EC or BIOS. The first use case for this is platforms that have AP wake events that go to the EC, for instance devices that use Deep S3 and have a limited set of wake pins. (such as Eve) This allows the AP to determine the exact wake source for an event so it can be logged and acted on by the AP if necessary. BUG=b:36024430 BRANCH=eve TEST=manual testing on eve with trackpad and dsp wake events Change-Id: I48d94014c00dc1dad098ab96af0ddc7860229762 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/555632 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: add U2F supportVincent Palatin2017-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement U2F (universal second factor authentication) feature over TPM vendor commands. The raw U2F APDU as defined by the FIDO Alliance 'U2F Raw Message Formats' specification can be sent using the VENDOR_CC_U2F_APDU command. So the vendor command is taking a ISO7816-4:2005 APDU format frame as input as defined by the spec and returns another APDU using ISO7816-4 status code. The APDU is processed by the common U2F code using u2f_apdu_rcv(), this hardware specific code provides: - the user physical presence detection (done by the power button press) returned by the pop_check_presence() callback. - the connection to the cryptographic hardware to generate/derive the keys used by the U2F and individual attestation functions. This feature/vendor command has 3 modes: - disabled - U2F (only the commands/flags defined by the U2F specification) - G2F (the U2F commands plus some extensions for individual attestation) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=b:35545754 TEST=pass U2FTest and HIDTest. Change-Id: Ic2591f369763fb4ba67926e2b4a0c2cd35330a18 Reviewed-on: https://chromium-review.googlesource.com/518139 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add U2F implementationVincent Palatin2017-06-293-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | Add the common code to support FIDO U2F (Universal second factor authentication) protocol implementation: the APDU parsing and standard commands execution, plus a few non-standard flags and hooks. The u2f.h header is the unmodified copy from the U2F v1.1 Specifications archive. Mostly copied over from the cr52 code-base. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=b:35545754 TEST=with follow-up CLs, run U2FTest on Eve. CQ-DEPEND=CL:*390230 Change-Id: I636d4a77ea69d69b5ab18a958e58ee6fcb2476bc Reviewed-on: https://chromium-review.googlesource.com/518136 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: Add base32 encodingRandall Spangler2017-06-282-0/+75
| | | | | | | | | | | | | | Base32 encoding is used to turn the RMA reset binary challenge/response into less-typo-prone text, at 5 bits per character. BUG=b:37952913 BRANCH=none TEST=make runtests Change-Id: I474750a20204ba353cea1e91982aa03e8071c0c2 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544177 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* vboot_ec:Read try slot from BBRAMDaisuke Nojiri2017-06-281-0/+1
| | | | | | | | | | | | | This patch makes EC read the slot to verify and jump to from the battery backed up RAM (BBRAM). BUG=b:38462249 BRANCH=none TEST=Boot Fizz Change-Id: I0c78861ea3ccdc45d0aa08e690e3a68f53658409 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/518255
* tcpm: add .release driver operation.Caveh Jalali2017-06-281-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | similar to the USB_PD_TCPC case, add release/init operations when the pd_task enters/leaves the PD_STATE_SUSPENDED state. one use case for PD_SUSPEND is to get exlusive access to the TCPC for things like firmware update, so the release/init operation is needed to get the TCPC and driver into a good state. updated all tcpm_drv style drivers. for backward compatibility, "old" drivers that may not handle init/release properly simply return EC_ERROR_UNIMPLEMENTED for tcpm_release(). pd_task() uses this as a signal that it should not try to re-init() the driver. TEST=tested in combination with follow-on CLs to do TCPC firmware update on electro. also built for kevin, eve, sand which are some of the other boards using these drivers. "make buildall -j" passes. BRANCH=none BUG=b:35586896 Change-Id: I3d2964a79e710428f7a6e7004d68ab424af85be8 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/544660 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Make system stay off after clean shutdownDaisuke Nojiri2017-06-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets/clears RESET_FLAG_AP_OFF on S5<->S3 transitions. It's set when the system gracefully shuts down and cleared when the system boots up. The result is EC tries to go back to the previous state upon AC plug-in on battery-less systems. This is required for digital signage and kiosk. This also reverts: CL 514209, 486946, and 486945. BUG=b:37536389 BRANCH=none TEST=Tested as follows: A. Boot to S0 A.1. Unplug AC while system is in S0 then plug in - PASS A.2. Unplug AC while system is in S3 then plug in - PASS A.3. Press recovery+power in S0 - PASS A.4. Press recovery+power in G3 - FAIL (To be fixed) A.5. Execute reboot console command - PASS A.6. Execute reboot OS command - PASS A.7. Execute reboot console command in G3 - PASS B. Boot to G3 B.1 Unplug AC while system is in G3 then plug in - PASS B.2 Unplug AC after B.1 then plug in - PASS B.3 Shutdown by power button on recovery screen then unplug plug in AC - PASS B.4 Execute reboot ap-off console command - PASS B.5 Execute shutdown command from OS then plug in AC - PASS Change-Id: Iaa6f930585050fdd3511c711b449dff47525066d Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/517287 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* vboot: Add vboot for EC by ECDaisuke Nojiri2017-06-282-0/+22
| | | | | | | | | | | | | | | | | This patch adds vboot for EC by EC (vboot EC) for x86 systems. When ec is transitioning s5->s3, it checks the power supply is enough to boot AP or not. If not, it runs other checks and may finally validate and jump to a RW image. BUG=b:38462249 BRANCH=none TEST=Boot Fizz on barrel jack and type-c charger. Change-Id: I5988b0595976370c5303c45541702ae89d86fc97 Reviewed-on: https://chromium-review.googlesource.com/518254 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* system: Add simplified sysrqDaisuke Nojiri2017-06-231-0/+5
| | | | | | | | | | | | | | | | | | | | On a keyboard-less, volume-button-less board, we support simplified sysrq handling. For Fizz, we use the recovery button to trigger sysrq event and holding it down to trigger warm reset. BUG=b:38418116,b:38417391 BRANCH=none TEST=On Fizz, try 1. Press recovery button and release -> sysrq sent 2. Press and hold recovery button -> warm reset 3. Press recovery button and power button -> enter recovery mode Change-Id: If8760319dba3df4545e9805b396ac89c241dae80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/537817 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cleanup: Remove big and pit boardsShawn Nematbakhsh2017-06-222-314/+0
| | | | | | | | | | | | | | | | | Remove big and pit boards along with several now-obsolete CONFIGs / source files. BUG=chromium:735109 TEST=`make buildall -j` BRANCH=None CQ-DEPEND=CL:544681 Change-Id: Ieb784bd36157fd1f6240cd19de6e6d12191a8097 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/540667 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rwsig: Fix mapped read location for rwsig / pubkeyShawn Nematbakhsh2017-06-211-8/+10
| | | | | | | | | | | | | | | | | | | | Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not CONFIG_R*_MEM_OFF. The previous implementation happened to work for internal mapped storage (eg. stm32) but failed for external mapped storage which is copied to SRAM before execution (eg. npcx). BUG=b:62841029 TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump and sig verification continues to work on fizz and stm32. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7 Reviewed-on: https://chromium-review.googlesource.com/541861 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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