| Commit message (Collapse) | Author | Age | Files | Lines |
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This adds the "i2cspeed port [speed]" console command. If only the port
number is given, then the current port bus speed is reported. With 2
arguments, the port bus speed is changed. Valid speeds are 100, 400,
1000 and the unit is kHz.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: I7ca6b2c7a8fd9abe8e8ec77e4d1702529b297fe8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181504
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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32 bit processors don't all allow left shift of
64 bit values. So add this to make it work with
32 and 64 bit processors.
uint64_t bitmask_uint64(int offset);
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: I114111c4774bb935a35c7711821b1f2f2f9c037d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182630
Tested-by: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Yuval Peress <peress@google.com>
Reviewed-by: Yuval Peress <peress@google.com>
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Many platforms have requirements to support more than one charge
source (eg. pirika). It can't be supported by just enabling two
different CONFIGS as that can lead to conflicts.
Eg.USD_PD_VBUS_DETECT_TCPC vs USB_PD_VBUS_DETECT_DISCHARGE.
This change provides a framework that supports two different charger
sources in the same build. Please see the CL for relevant logs.
BRANCH=None
BUG=b:194375840
TEST=make -j buildall
Signed-off-by: Parth Malkan <parthmalkan@google.com>
Change-Id: I309cc5930233983e615d90a4290fc749abf7aa2d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088232
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Thermistor drivers now query the device tree for configuration.
Thermistor tests have been updated to be parameterized
on all thermistors enabled in the device tree.
BRANCH=none
BUG=b:184374937
TEST= 1) zmake testall
2) make runhosttests
Cq-Depend: chromium:3161332
Signed-off-by: Aaron Massey <aaronmassey@chromium.org>
Change-Id: Ic5330cd5c33e79e192428ca857651de9a225856e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133812
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Aaron Massey <aaronmassey@google.com>
Commit-Queue: Aaron Massey <aaronmassey@google.com>
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add register and value definition to tune usb and dp.
BUG=b:198258596
BRANCH=None
TEST=make -j BOARD=bugzzy
Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com>
Change-Id: I82808af8c2f53783a3157417063cf40e2df70ad6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139526
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Henry Sun <henrysun@google.com>
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This reverts commit f0985f8a11585f6a704aa94a8354bd5b934619ac.
Reason for revert: Issue is resolved after setting the Force BB Retimer GPIO
(GPP_E4) to 0. It is a coreboot change.
BUG=b:195375738
BRANCH=None
TEST=TBT enumerated no lane bonding issue is observed with above
coreboot code change with reverted EC WA.
Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.corp-partner.google.com>
Change-Id: I09a8a53aec9ba3757189a091606922bc7a133ba7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3162936
Reviewed-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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To support multiple OS and to reduce the BOM stuffing options on
Intel RVP, Packet mode GPIO is added on I/O expander hence added
overridable function.
BUG=b:200189880
BRANCH=none
TEST=make buildall -j
Change-Id: Ieea1129614258393f7c73712ed28ed50b9fbf8fb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087618
Reviewed-by: Li Feng <li1.feng@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Currently color map is reusing the same structure as the channel and
callback selection, which is a bit wasteful and somewhat confusing.
Split it to its own struct with just three uint8_t fields.
BRANCH=none
BUG=none
TEST=build only
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I56992fa9525db46980e450eb6569ba8291987b9b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168864
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yuval Peress <peress@google.com>
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API pd_get_am_discovery() sets the lock (task access bit) to keep track
of EC tasks accessing the pd port discovery data. If any of the task
access bits are set,EC host task typec discovery handler will return
EC_RES_BUSY to host, indicating discovery data is modified while copying
port discovery data to the host. Hence the lock/task access bit should
be set only when the port discovery data is modified by any tasks.
Setting of lock/task access is removed from pd_get_am_discovery() and
implemented new api pd_get_am_discovery_and_notify_access() for this.
pd_get_am_discovery() proto type is changed to return 'constant pointer'
which forces developers to use pd_get_am_discovery_and_notify_access()
when they intend to access and modify discovery data.
summary of changes implemented.
- Remove setting of task access bit from pd_get_am_discovery().
- modify pd_get_am_discovery() prototype to return constant pointer.
- implement new api pd_get_am_discovery_and_notify_access()
- Replace calls to pd_get_am_discovery() with new api
wherever discovery data is accessed and modified.
BRANCH=none
BUG=b:197466819 b:190390784
TEST=Verified 50 cold boot cycling with TBT device attached.
Device detected in every cycle.
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
Change-Id: I5b6f1f2b91d92ddbe58f3bf994f684abee948c02
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139858
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
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A field (cros_fwid_rw) was added to ec_response_get_version and the
version was updated to v1. Some system components that still use v0
of the version host command fail because the size of the response
does not match the updated ec_response_get_version struct.
Restore ec_response_get_version to match v0. Create a new
ec_response_get_version_v1 structure with the added v1 fields.
This allows legacy code to continue using ec_response_get_version,
which matches the expected response size for the v0 command.
BUG=b:188073399,b:200075921
TEST=EC console 'version' works
Legacy 'ectool version' works with old an new EC firmware.
New 'ectool version' works with old and new EC firmware.
BRANCH=None
Change-Id: I51a052a550c2460f2604da8e04fc43c36acba4d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169100
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:200046770
TEST=make buildall -j
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I5f1c228b44a64e9ceab4511713ac4cf70b24e116
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168032
Tested-by: Yuval Peress <peress@google.com>
Auto-Submit: Yuval Peress <peress@google.com>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
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Add guards to limit the long warm_reset handling only in SC7180, such
that the future generations, like SC7280, don't have it.
BRANCH=None
BUG=b:187980397, b:187098628
TEST=Built all the Chromium EC images and Zephyr EC images.
TEST=Modify a board to use the SC7280 CONFIG.
Change-Id: Iad011f58522641cde2f469f71114473476c53d67
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893070
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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The BB retimer may use a simple read/modify/write on its configuration
register to set HPD fields, rather than needing to rely on a call to a
full mux set later to achieve this. Introduce an API so boards using
the BB retimer may move to using this function.
BRANCH=None
BUG=b:195773400
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Iae87c0860350fed32f69e0ea3b6530cd7e5ba111
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163929
Reviewed-by: Keith Short <keithshort@chromium.org>
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Since the drivers are now taking a mux_state_t set of flags to update,
go ahead and unify the usb_mux API this way as well. It makes the
parameters more apparent than the 1/0 inputs, and aligns the stack to
use the same parameters.
BRANCH=None
BUG=b:172222942
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ie943dbdf03818d8497c0e328adf2b9794585d96e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095438
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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If set, this option will prevent saving General Purpose Registers
during panic. When software panic occurs, R4 and R5 will be saved,
because they contain additional information about panic.
This should be enabled on boards which are processing sensitive data
and panic could cause the leak.
BUG=b:193408648
BRANCH=none
TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo'
to check what was saved. When CPU exception occurred registers
R0-R12 should be set to 0. In case of software panic, R4 and R5 can
contain panic reason and additional information.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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EC version does not follow the the AP and OS version. This causes
confusion during development. This change augments the EC version output
to include the CrOS FWID when available. The CrOS FWID will be missing
when the CrOS EC is built outside of cros_sdk. When CrOS FWID is missing
'CROS_FWID_MISSING' will be used.
Zephyr/zmake support will be added later, CROS_FWID32 is set to
'CROS_FWID_MISSING' in zephyr builds until then.
BUG=b:188073399
TEST=version
21-05-20 16:43:18.627 Chip: Nuvoton NPCX993F A.00160101
21-05-20 16:43:18.631 Board: 1
21-05-20 16:43:18.631 RO: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.634 guybrush_13983.0.21_05_20
21-05-20 16:43:18.639 RW_A: * guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.641 * guybrush_13983.0.21_05_20
21-05-20 16:43:18.644 RW_B: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.644 guybrush_13983.0.21_05_20
21-05-20 16:43:18.647 Build: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.651 guybrush_13983.0.21_05_20 2021-05-20
21-05-20 16:43:18.657 16:31:19 robbarnes@robbarnes0
ectool version
RO version: guybrush_v2.0.8770+f47439f75
RO cros fwid: guybrush_13983.0.21_05_20
RW version: guybrush_v2.0.8770+f47439f75
RW cros fwid: guybrush_13983.0.21_05_20
Firmware copy: RO
Build info: guybrush_v2.0.8770+f47439f75
guybrush_13983.0.21_05_20 2021-05-20 16:31:19 robbarnes@robbarnes0
Tool version: 1.1.9999-f47439f @robbarnes0
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ief0a0c6e9d35edc72ac2d4780ee203be41d7305f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2894145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Put list_activities in common code, as it is used by both BMI160 and
BMI260 driver.
Fixes cb3771973de ("Coachz: MotionSensor: Avoid redefine gesture function list_activites")
Fixes fc298a0ada0 ("driver: bmi260: integrate body detection")
BUG=b:195908820
BRANCH=trogdor
TEST=buildall
Change-Id: I05591954c825802502328c842b03e8934c497f08
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3150056
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Don't clear discovery data when resetting active modes during mode exit.
BUG=b:141363146
TEST=make buildall
BRANCH=firmware-volteer-13672.B-main
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I8052641bb850ce8486eb9c82641b41880cb97d65
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3123837
Reviewed-by: Diana Z <dzigterman@chromium.org>
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To avoid the I2C address contention between multiple I2C devices
on same bus, added code to support multiple I2C addresses for
it8801 I/O expander.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I6985973f9ae3ce91383d3b568a851169e6a308af
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3115426
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Li Feng <li1.feng@intel.com>
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MECC1.1 is defined for ADL+ platforms. To simplify the the BOM
stuffing options and also to remove dependency on H1 by MECC vendors,
H1 is added on RVP as AIC.
BUG=b:197659347
BRANCH=none
TEST=make buildall -j
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Change-Id: I5c3b4b2b2a116ec8dc5a7448c71a6b8654a78bba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114218
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Li Feng <li1.feng@intel.com>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The register for enabling USB register clock appears to have been
identical across F0, F3, and G4 families, but for L5 it is
different. Rather than having #ifdef in usb.c (as I recently
committed), this CL will move the clock logic into
clock_enable_module() where it arguably belonged all the time.
Additionally: Some of the chip families make use of a clock_mask in
their implementation of clock_enable_module(), but since the module_id
enum has more than 32 value, until now, some values (among those
MODULE_USB) would result in overflow, causing new_mask to be identical
to clock_mask, and the USB case could have never been reached.
BUG=b:192262089
TEST=Compile servo_v4 without linker errors
BRANCH=none
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Add a function that will provide information if interrupts are enabled.
This information will be used to fix shortcomings in common code for
UART buffering and usleep().
BUG=b:190597666
BRANCH=none
TEST=make -j buildall
TEST=make runhosttests
TEST=Note for running tests: this patch only adds function
implementation so, to test this it is necessary to add some code
which uses the function eg. console command which prints
information if interrupt is enabled.
Minute-ia core: It is necessary to compile firmware for
ISH (Intel Sensor Hub) which is available on drallion board
(eg. chromeos6-row1-rack9-host19). Firmware must be placed in
/lib/firmware/intel/drallion_ish.bin (partition must be writeable,
if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock
it, don't forget about reboot). After copying firmware to
/lib/firmware/intel/ it is necessary to reboot DUT. After reboot
use `ectool --name=cros_ish version` to check if correct version
is running.
NDS32 core. This core is used in it8320dx chip which is present in
ampton (octopus family). EC can be compiled using
'make BOARD=ampton' and flashed using
'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to
be disabled using 'set_gbb_flags.sh 0x200'
Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which
is based on risc-v. EC can be compiled using 'make BOARD=hayato'
and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC
software sync needs to be disabled using 'set_gbb_flags.sh 0x200'
Cortex-M, this is the most common core. Just compile EC for
platform which contains Cortex-M core (eg. bloonchipper) and test
if it works.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add hibernate flag. Before system reset, it should be distinguished as
hard reset or hibernate reset and saved in BBRAM.
BUG=none
BRANCH=none
TEST=none
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: I0e06f3d1bea89ead1795cc07677e22e841643a97
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139528
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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BUG=none
BRANCH=none
TEST=none
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
Change-Id: I3999dbd4300eca80effed7a2d42e153c0ad59543
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140203
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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Add BB retimer emulator on i2c bus. Emulator properties can be defined
using device tree or runtime emulator API. Emulator checks if RO
registers and reserved bits are accessed correctly. API allows to set
custom read/write i2c messagess handlers to emulate complex behaviour.
BUG=b:184856919
BRANCH=none
TEST=none
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
Change-Id: I4b641a90e6fb55e89aaee388c0ac04ab7bf367ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3110085
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
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Return the status of the init function. This will be used in
testing to verify that initialization was correct.
BRANCH=none
BUG=b:184856083
TEST=make buildall -j
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I578b32b24b3ee59abf646307fb9670d2db74fe3b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133624
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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Support dynamic PDO selection CONFIG_USB_PD_DPS.
This config controls the charging voltage and power according to the
input power and battery configuration.
DPS would continuously evaluate the system load and current charging
voltage, and decide a new one by below:
1. If the PDO can fulfill system desired power.
2. If the PDO is efficient for the battery configuration.
To detect if the system load cannot be fulfilled by the current PDO,
it checks:
1. if the input current closes to the PDO current limit.
2. if the input power closes to the PDO maximum power.
To detect if the system load can be fulfilled by a more efficient PDO,
it checks:
- if the voltage of a new PDO is closer to the battery voltage than the
current PDO, and the power is able fulfill the system load.
BUG=b:169532537
TEST=1. tested on asurada, the charging voltage is able to switch to
different PDOs under different system loads
2. tested that the DPS is able to switch charge port
(e.g. C1 12V -> C0 9V) based on the provided PDOs.
BRANCH=asurada
Change-Id: I7c7706b331dc0d4f8ac68569dc7ed852fc9308e3
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2897064
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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There's a bug in the chip_revision calculation. Also, add a missing
include which causes a warning during build.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Id636f4abcfffc0158d879d4b9333c7cb3ac1ee21
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133800
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Yuval Peress <peress@chromium.org>
Auto-Submit: Yuval Peress <peress@chromium.org>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Verify that we can call host commands from driver tests by adding a test
that calls the EC_CMD_GET_PROTOCOL_INFO host command. Add a few
convenience functions to host_command.h when building with CONFIG_ZTEST
enabled. Also, add eSPI emulator to support the test.
Coverage:
- lines 17.4% -> 17.8%
- functions 21.4% -> 22.0%
BRANCH=none
BUG=b:189954415
TEST=zmake configure --test zephyr/test/drivers
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Ib9e750eeab555ea629a560cbf3beed28e346c460
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3031842
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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As a followup to CL:3104290, give the TCPCI TRANSMIT and
RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used
for receiving, not just transmitting. Fix lint errors thus revealed.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995
Reviewed-by: Keith Short <keithshort@chromium.org>
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When using ztest_unit_test the default setup/teardown functions should
be before_test() and after_test().
BRANCH=none
BUG=none
TEST=make buildall -j
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Ia1a65923a39d3f193a9cedecdc9d716dcf136eb6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3132306
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Since we have definitions for HPD IRQ and level in the mux flags, extend
this to the HPD update function in the usb_mux structure as well.
BRANCH=None
BUG=b:172222942
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I19c3a65fc821a341338d73fabd7876339b37fe7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095437
Reviewed-by: Keith Short <keithshort@chromium.org>
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Add board_get_vbus_voltage to get vbus voltage by board, for
ADC_VBUS maybe is only for one typec port when the DUT supports
multiple typec.
BUG=b:196001868
BRANCH=none
TEST=show correct C1 vbus voltage on tomato
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: Ia567ec3bddf4f62a08c9902b4f0721783f2c07ff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084403
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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This adds the CONFIG_ADC_CHANNELS_RUNTIME_CONFIG config option to allow
the adc_channels array to be tweaked at runtime.
BRANCH=none
BUG=b:183452273,b:181271666
TEST=buildall passes
Change-Id: I1241012b6e36c19baa7fe80853a6c6de4affeefa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3116990
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This reorganizes adc.h and adc_chip.h so that general code only needs to
know about adc.h. adc_chip.h is now included by adc.h directly and does
not need to be included in general code.
BRANCH=none
BUG=b:181271666
TEST=buildall passes (with next patch in series)
Cq-Depend: chromium:3120316
Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL adds a new overridable function to allow boards more control
over the USB mux. For type-c only connections, the mux may only be set
one time based only on data role.
The default function returns false, so only boards which override this
function will be affected.
BUG=b:195042155
BRANCH=quiche
TEST=Verfied that when I connect USBC only source on gingerbread that
the TUSB1064 usb mux gets configured to enable USB3.1 mode.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I5cc7466d2d13c46b1ff6cfc48af577559591f6e4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3119224
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Some platforms (e.g. servo_v4(p1)) are designed to act only as a
UFP considering superspeed terminations. Add config option to properly
manage usb superspeed muxer for such.
BUG=b:137887386,b:182419010
BRANCH=main
TEST=With servo_v4p1 connected to the DUT, unplug and replug CHG couple
of times in order to force PR_SWAP on DUT port. Each time verify
on the DUT console, whether all USB3 devices are visible. They
should be, since servo is trying to perform DR_SWAP when it acts
as a SRC.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0a7756f0bb2192795b7489334ed01d317d3e54ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3094246
Reviewed-by: Michał Barnaś <mb@semihalf.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
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Add macros to convert to and from milli kelvin and various temperature
units. Utilize round_divide for more accurate conversions.
BUG=b:176994331
TEST=Unit test
BRANCH=None
Change-Id: Ie6750b9d2d2b8093fdf9c14f904382e91d8d95bb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078051
Reviewed-by: Keith Short <keithshort@chromium.org>
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The current API for system_get_scratchpad mixes the status and the value
being read. Update the signature to allow both.
BRANCH=none
BUG=b:195481980
TEST=make testall && zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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As noted in the bug, this macro is an antipattern. Drop it.
BUG=b:197159539
BRANCH=none
TEST=zmake testall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I2fa6515149ff31ae650ed4f3fdc65b111f62c5b0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104788
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Convert usages of this enum to tcpm_sop_type.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I5fed273d72e7ad0e191db0cb0d121b70bdd9ecdb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104291
Reviewed-by: Keith Short <keithshort@chromium.org>
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Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be
used for Rx as well. Describe it in comments. This prepares to
consolidate enum pd_msg_type into this enum.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290
Reviewed-by: Keith Short <keithshort@chromium.org>
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Previously, functions for reading board version and sku id were defined
in board.c files which are not compiled in Zephyr builds.
Logic from board.c files should be moved to the DeviceTree files.
This commit adds support for defining board version and sku id
pins and numeral system used to decode them.
BRANCH=main
BUG=b:194136536
TEST=Call system_get_sku_id and system_get_board_version
on CrOS EC and Zephyr, values should be correct and
the same on both versions
Change-Id: I61b5e205cb2a2299ad86c5dff38c05a9659eb2d3
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3048102
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
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Add a driver for writing Skin Temperature Tracking (STT) sensor
readings to the SB-RMI interface. STT readings are used to maximize
the SOc performance while keeping the skin temperature within
specification.
BUG=b:176994331
TEST=Build and run on guybrush
BRANCH=None
Change-Id: If655545158e7dc05946bc67686b1b0b40a40a713
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078050
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
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Add Side-Band Remote Management Interface driver. SB-RMI can be used to
manage power limits of the SOC. SB-RMI uses a soft mail box for
executing transactions.
BUG=b:176994331
TEST=Build
BRANCH=None
Change-Id: Ie185985e4c8d2c2d915b2ae2447709ddc16adda6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078049
Tested-by: Rob Barnes <robcb85@gmail.com>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Fanli Zhou <fanliccc@gmail.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
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Some muxes may need to be re-set after they've power cycled, and many
muxes are tied to the S5 power rails. Introduce a flag which can be
used to indicate a mux needs to re-run init and is no longer in LPM
after the G3 state has been hit.
BRANCH=None
BUG=b:195045790
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I8bd4184dbea629edf106dbee32f811620ebda0dd
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093086
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The latest app note indicates the ps8815 firmware may take up to 50ms to
be ready.
BRANCH=none
BUG=b:186189039
TEST=buildall passes
Change-Id: Ibc5ee2e6030d19b91d6c0b8a493aa05dd31c77e4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087983
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Currently, only the virtual mux driver uses the mux ACK feature, but the
actual wait for the host command ACK is a part of the usb_mux general
code. Generalize this mux ACK wait so it's available if needed in the
future for more muxes.
Additionally, moving this wait out of the mux set will allow us to lock
the muxes intelligently between tasks, without keeping the muxes locked
during the inactive ACK wait.
BRANCH=None
BUG=b:172222942,b:186777984
TEST=tast typec.Mode*.manual on voxel
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I61a043425a482cc6f3170548c888d91ec20c2a82
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078411
Reviewed-by: Keith Short <keithshort@chromium.org>
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Add the standard string function strcspn. strcspn calculates the length
of the initial segment of s which consists entirely of bytes not in
reject.
BUG=None
TEST=make run-utils_str
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I3eb9a4fff42cb0fdcdb288d00f8070e0f22b2179
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3057730
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
by hardware, it will add several system clock cycles delay between CS
deassertion to CS assertion at the start of the next transaction, this
guarantees SPI back to back transactions, so 1ms delay can be removed
to optimze timing.
BUG=none
BRANCH=none
TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job
save 720ms as EC performs 180KB RW code's SHA256 hash computation
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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