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* ish: infrastructure changes to support ish5.4 PMLeifu Zhao2020-02-271-0/+6
| | | | | | | | | | | | | | | | | | Infrastructure related changes to support enabling power management for ish5.4 on tgl rvp platform. BUG=b:149238813 BRANCH=none TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* usb_set_suspend: Use "enable" consistentlyAbe Levkoy2020-02-271-2/+2
| | | | | | | | | | | | | | The port is enabled when suspend is not enabled and vice versa. Avoid confusing these idioms. BUG=none TEST=make buildall BRANCH=none Change-Id: I3063793334ac875afee8a176f96625e8903d2694 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057979 Reviewed-by: Keith Short <keithshort@chromium.org>
* volteer: Update USB C1 reset for next buildstabilize-volteer-12931.B-masterKeith Short2020-02-261-0/+3
| | | | | | | | | | | | | | | | Update the GPIO assignment for the USB_C1_RT_RST_ODL signal for the next board build. BUG=b:144933528, b:148243971 BRANCH=none TEST=make buildall TEST=Check unassigned board ID or board ID=0 uses legacy GPIO setting. Otherwise new GPIO setting is used. Change-Id: I4621e039e4461a4e10ab87bc2d4e000b5dcaa885 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057496 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TUSB544: Add driverDiana Z2020-02-251-0/+1
| | | | | | | | | | | | | Driver code for the TUSB544 redriver BRANCH=None BUG=b:149561847 TEST=builds Change-Id: I391d6d264ff9d326c2d45569124dd1366f892812 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062766 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv1/v2: Move hex8tou32 and remote_flashing to common fileSam Hurst2020-02-251-0/+25
| | | | | | | | | | | | | BUG=chromium:1021235 BRANCH=none TEST=make buildall -j Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: Ia243d5062c77d8f6b8299fbd131cabfdbcffb01e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2070452 Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Sam Hurst <shurst@google.com>
* gpio: Free gpio.inc from oppressive orderCraig Hesling2020-02-252-14/+140
| | | | | | | | | | | | | | | | | | | | | | | | | This CL enables gpio.wrap to correct the order of all declaration in gpio.inc. Previously, gpio.inc had to be written such that GPIO_INTs were at the top of the file, GPIOs following GPIO_INTs, and then IOEX_INTs before IOEXs declaration. This ordering was required because the signal name enums were used to index into the interrupt handler table. See crrev.com/c/263973 (gpio: Refactor IRQ handler pointer out of gpio_list). This constraint not only limited the creativity and art of an individual crafting a gpio.inc, but also made recursively including gpio.inc's (for baseboard or other) messy and ugly. BRANCH=none BUG=none TEST=make buildall Change-Id: Ie4531b95b65728b646087f00e9434f4cfdc49287 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056498 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* servo_micro: move ite flashing codeJett Rink2020-02-252-0/+33
| | | | | | | | | | | | | | | | In preparation for servo_micro and c2d2 to sharing the ite, i2c flashing code, move it to a stm specify common file. It is STM specific because it explicitly uses STM registers to accomplish the non-compliant i2c waveforms needed to put the ITE EC into flash mode. BRANCH=servo BUG=b:148610186,b:79684405 TEST=flash ampton with servo_micro using this code Change-Id: Ia0f3f944df2f8a8ad47ea5a62c5f0edae2c71943 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064592 Reviewed-by: Diana Z <dzigterman@chromium.org>
* EFS2: Sync cr50_comm_err with Cr50's definitiondnojiri2020-02-241-2/+3
| | | | | | | | | | | | | | | | | This patch syncs enum cr50_comm_err with the one defined in cr50_stab. Signed-off-by: dnojiri <dnojiri@chromium.org> BUG=chromium:1045217 BRANCH=none TEST=Boot reworked Helios and verify software sync works. Change-Id: I2848a2d03fc90cbc9b292edaee1760e9ed32298d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2069029 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* TCPMv1/v2: Move pd_set_polarity() to common fileVijay Hiremath2020-02-242-8/+8
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: Idf6908bfc3e79a960a7de6e4249c2f50b41b56e6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2052645 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMV1/2: Make the PD Config Flags more consistentSam Hurst2020-02-221-15/+53
| | | | | | | | | | | | | | | | | | | | The current use of the PD Config Flags are a bit confusing and has been changed to the following: The CONFIG_USB_POWER_DELIVERY flag is used to enable and disable the TCPMv1 and TCPMv2 stacks. And when CONFIG_USB_POWER_DELIVERY is enabled, one of the following must be enabled: CONFIG_USB_PD_TCPMV1 - legacy power delivery state machine CONFIG_USB_PD_TCPMV2 - current power delivery state machine BUG=b:149993808 BRANCH=none TEST=make -j buildall Change-Id: Ie3f8615a75b15b4f1c703f57f3db9e152a471238 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068519 Reviewed-by: Diana Z <dzigterman@chromium.org>
* power/common: Add board specific API for 5V controlAseda Aboagye2020-02-211-0/+10
| | | | | | | | | | | | | | | | | | | Some boards need different mechanisms to enable/disable the 5V rail that's not simply setting the PP5000_EN GPIO. This commit adds a new board specific API to control the 5V rail. If a board needs something more complex, they should define `board_power_5v_enable`. BUG=b:149794574 BRANCH=None TEST=Add definition for waddledoo, build and flash, verify that sub-board 5V is turn on as well. Change-Id: I333e3fb8f2b4e7f1907c792c0e35581150857f17 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065494 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* intel_x86: Add CONFIG_BOARD_HAS_AFTER_RSMRSTAseda Aboagye2020-02-212-0/+16
| | | | | | | | | | | | | | | | | | | Some x86 boards need to perform some workarounds after handling RSMRST_L, therefore this commit adds a CONFIG_* option to enable this, CONFIG_BOARD_HAS_AFTER_RSMRST. A board callback, board_after_rsmrst() will be called after RSMRST is changed. BUG=b:148688874 BRANCH=None TEST=Enable CONFIG_* option, verify that callback is called once RSMRST changes. Change-Id: Ic6b6b4a0f23639e3fd4d9e69c95b3d94e44a2162 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2058693 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* it83xx/dac: add DAC moduletim2020-02-213-0/+5
| | | | | | | | | | | | | | | | | | The DAC module has four channels. We can set output voltage when DAC channel is enabled by this driver. BUG=b:149094279 BRANCH=none TEST=The console command #dac set as follows: read: dac [ch] write: dac [ch] [voltage] [ch]:2-5, [voltage]:0(disable)-3300 Change-Id: I8e815cb5bc749467581d5f771fd6f9e0995fca3b Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2046685 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Servo: Adds persistent storage of MAC addressBrian J. Nemec2020-02-213-0/+42
| | | | | | | | | | | | | | | | | | | | | | | Adds a field to the persistent storage to store the MAC address of the device. This is enabled on ServoV4 in order to store the MAC address for the integrated ethernet port. Added a console command to set and load this value. BUG=b:149506580 TEST=Verified setting and loading the MAC address using: 'macaddr set 12:34:56:78:90:ab' and 'macaddr' or 'macaddr load' Verified that MAC addresses over 19 characters long return an error response and not update the MAC. Verified no set serial number will return the uninitialized string. Verified that the MAC address can be updated independently of serialno Verified that the persist_state fields restore during firmware updates Change-Id: I8425ce9e13322e99a4f59df444ea0dc73821aa6b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2063330 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* nct3807: potential connection cleanupDenis Brockus2020-02-201-12/+15
| | | | | | | | | | | | | | | | | | | | I changed TCPMv2 to call tcpm_set_new_connection instead of tcpm_set_cc when connecting at the parent state for a new connection type. This allows the NCT3807 to clear out DRP and set the correct connection instead of clobbering what the hardware determined to be correct and setting it to an open listen. BUG=b:149593609 BRANCH=none TEST=verify USB-C Change-Id: I7402d3417a14fdc4158636e4716ef7fbdf4fa4a3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064184 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* TCPMv1/v2: Move pd_is_try_source_capable() to common fileVijay Hiremath2020-02-191-0/+5
| | | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I79f75d23f6091a264c11b4da6cf0cea26205df60 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2052648 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2Ruibin Chang2020-02-191-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PD driver for chip it8xxx1/8xxx2 series. BRANCH=none BUG=none TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1 (set cc toggle by console cmd): 1.pin configuration console cmd "gpioget" check gpio settings. memory dump check cc pin alternate settings. 2.Tx data error handle Message discard, No GoodCRC, Tx not enable, Timeout errors happen, corresponding INT will be triggered then do properly handle. 3.basic pd connection SNK:connect with adaptor, request max power (15V,3A), state SNK_READY. SRC:enable DRP role, connect with dongle, provide power (5V,1.5A), source Vconn 5v, get ack of cable discover id, state SRC_READY. 4.pd module disable SNK:connect with adapter. console cmd "hibernate sec", driver disable pd module, check still connection with adapter via dead battery rd. And when resume from hibernate, pd init can re-enable pd module, re-connect with adapter. SRC:connect with dongle. console cmd "hibernate sec", driver disable pd module, check cc pin (not Vconn source pin) volt power down to ~0v. And when resume from hibernate, pd init can re-enable pd module, re-connect with dongle. 5.Tx hard reset console cmd "pd port hard", check hard reset message by lecroy analyzer. 6.Tx cable reset check cable reset message by lecroy analyzer. 7.SOP' enable SRC:connects to SNK via E-mark cable. Source Vconn successfully, and receives cable's ack of discover id request. Not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 8.power role swap console cmd "pd port swap power", check pd protocol by lecroy. Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: remove tri-state polarityDenis Brockus2020-02-151-7/+1
| | | | | | | | | | | | | | | | | | TCPCIr2 had an issue with setting CC coming out of DRP that if the polarity was not retained that the connection dropped back to OPEN. Unfortunately this change broke many of the other TCPCI implementations. I am working on a different method of dealing with coming out of DRP and this is no longer needed. BUG=none BRANCH=none TEST=verify USB-C is working Change-Id: Ifa8f26d417df2f5d5f41a23fbf7e6f9129031e94 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056968 Reviewed-by: Jett Rink <jettrink@chromium.org>
* nct38xx: auto-toggle exit cleanupDenis Brockus2020-02-152-21/+12
| | | | | | | | | | | | | | | | | | Don't set the polarity behind the back of the PD stack. Just clear the DRP and leave the CC lines so they look just as we found them. This will allow TRY to work and we will no go OPEN because we set the CC lines to something that was not expected. BUG=b:149415919 BRANCH=none TEST=verify USB-C connections are working Change-Id: I766514bd46922000ea8916d61d00265e7e5e4fd4 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2053461 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* tcpci: Rename TCPC_FLAGS_TCPCI_V2_0 to TCPC_FLAGS_TCPCI_REV2_0Edward Hill2020-02-141-2/+2
| | | | | | | | | | | | | | | | | | Align naming of TCPC_FLAGS_TCPCI_V2_0 to match spec: "USB Type-C Port Controller Interface Specification" "Revision 2.0, Version 1.0" BUG=none BRANCH=none TEST=none Change-Id: I27752847581e449c3a2f6be438704d3e514c937d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057375 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Temp sensor: Remove action_delay_sec fieldDiana Z2020-02-141-3/+0
| | | | | | | | | | | | | | The action_delay_sec field hasn't actually been referenced by any code since 2013. Removing the corresponding struct field. BUG=None BRANCH=None TEST=builds Change-Id: Ia7334c26b85d0161ff61bb51fbdda61bb921595a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054945 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv1/v2: Move PD & Partner type detection code to common fileVijay Hiremath2020-02-141-2/+2
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: Icb9dfe998df889e8e2d6de7776d9889295115708 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2052644 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Reduce number of arguments of pd_build_request()Vijay Hiremath2020-02-142-14/+3
| | | | | | | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=Manually tested on Volteer 1. When only one charger connected: Able to negotiate to PD max. 2. When two chargers are connected (one on each port): Non charging port is rejected Swaps the charging port based on charger's priority Change-Id: Ib7fdc5d31bf36189a85f8cd3217bec78f83a9efe Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051318 Reviewed-by: Keith Short <keithshort@chromium.org>
* tcpmv2: make connect after auto-toggle driver specificDenis Brockus2020-02-132-0/+23
| | | | | | | | | | | | | | | | | | | | | nct38xx needs to have the cached polarity set in order to leave DRP mode without going back to an OPEN line. Other TCPCI implementations break when this happens. So moved it to a driver specific function instead TODO(b/149415919): Consider trying to clear the DRP mode instead of changing the polarity BUG=b:149311437 BRANCH=none TEST=verify charger functions on Trogdor Change-Id: I5092a468d860b573a6e5acaf7c013b3425916efb Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2050336 Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* common: Migrate online calibration to own moduleYuval Peress2020-02-131-0/+29
| | | | | | | | | | | | | | | This change moves the code that handles caching the temperature (which is the first step in online calibration) into a new compilational unit. TEST=None BRANCH=None BUG=b:138303429,chromium:1023858 Change-Id: Ib1fe3d2234dc2436e2bbfd4febd22196e5cdafef Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906340 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* TCPMv1/v2: Move pd_process_source_cap() to common fileVijay Hiremath2020-02-121-0/+10
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I6bd6b5875a322ca4ba6d77a4cfc96a72630e5f5c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051220 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move pd_check_requested_voltage() to common fileVijay Hiremath2020-02-121-1/+1
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I5ba854552b5c6124e3c6758273651edc0e3c23ae Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051214 Reviewed-by: Keith Short <keithshort@chromium.org>
* EFS2: Implement Early Firmware Selection ver.2Daisuke Nojiri2020-02-093-1/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring the benefts to Chromebooks, which are: - Reduce RO dependency and presence. Allow more code to be updated in the fields. - Remove jumptag and workarounds needed for late sysjump. Major imporvements over v1 are: - No A/B slot required. - No signature in RW or public key in RO. - Rollback-attack protection. - Verifies only RW being used instead of whole RW section. For battery-equipped devices, additional benefts are: - Immediate boot on drained battery. - Support recovery mode regardless of battery condition. - Faster charge in S5/G3. EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm). EFS2 is documented in go/ec-efs2. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1045217,chromium:141143112 BRANCH=none TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode. TEST=Wake up EC from hibernate. TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep. Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* common: Implement accelerometer calibrationYuval Peress2020-02-082-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change implements the hybrid accelerometer calibration algorithm described in https://drive.google.com/corp/drive/u/0/folders/13k8AWvVkCg8KUr1HhD2qv6_ob1ixgCbE 1. Waits until the device is still 2. Adds a still sample to an orientation accumulator - If the new sample is close to an existing one, they're merged. - If the new sample is unique, it is added to the list of orientations in a FIFO manner (may be evicting an older sample). - Once enough orientations have been gathered, run the kasa algorithm. - The kasa algorithm should yield a radius that's near 1g, since all the samples were added when still. If this isn't the case, we fall back on newton's method (which takes longer). BUG=b:138303429,chromium:1023858 BRANCH=None TEST=buildall with new unit tests Change-Id: I98bb0d365017d8a916b008c7c0c263345a9cddac Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879716 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* fpsensor: Refactor fpsensor tests into separate binariesTom Hughes2020-02-071-0/+18
| | | | | | | | | | | | | | | | | | | | | | | Using separate test binaries helps to prevent state from one set of tests accidentally leaking into other tests. Ideally all unit tests should be completely independent. Since there's a lot of global state in the fpsensor code the separate test binaries should help prevent the state from leaking across tests as we continue to add more. Also, by having a 1:1 correspondence between test binaries and test files, it's clearer what file (and functionality) each set of tests is targeting. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I937a5ffebfe61aa711efbbc2467d15d514fcfbae Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1832748 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Yicheng Li <yichengli@chromium.org>
* TCPMv1/v2: Move "pdcable" console command to common fileVijay Hiremath2020-02-071-0/+10
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I7f78efeb74536d5d6c5dd0b4bd5f32325c1500ec Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036604 Reviewed-by: Keith Short <keithshort@chromium.org>
* g: add gpio_set_wakepin() to configure wake pinsMary Ruthven2020-02-071-2/+18
| | | | | | | | | | | | | | | | | | | | | | Cr50 needs a cleaner way to enable and disable wakepins. This change adds gpio_set_wakepin() to enable the wake pin or disable. The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting wake-pin configuration. This patch increases the flash usage by 16 bytes. BUG=b:35587259 BRANCH=cr50 TEST=verify pinmux has the same output before and after the change on octopus. Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* common: Implement newton sphere fitYuval Peress2020-02-062-0/+124
| | | | | | | | | | | | | Add implementation of Newton's method for sphere fitting. BUG=b:137758297,chromium:1023858 TEST=Added new unit tests BRANCH=None Change-Id: Ic78ec4f8a8c2f57ddfa1d5220861bf5c06981ad8 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869730 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common/vboot: Add rwsig info commandTom Hughes2020-02-062-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rwsig info command provides additional details on the verified boot key used to sign the RW firmware. The information about the key can be used by factory tests to validate that the factory is flashing firmware that is signed by the expected key. In addition, we refactor the "rwsig"-related commands into a generic "rwsig" command that takes additional subcommands. This allows adding an "rwsig dump" command that allows displaying individual fields, which is useful in scripts and tests. "rwsigstatus" becomes "rwsig status" "rwsigaction" becomes "rwsig action" The old commands are preserved for backward compatibility. BRANCH=none BUG=b:144958737 TEST=(kohaku) $ ectool --name=cros_fp rwsig info TEST=(kohaku) $ ectool --name=cros_fp rwsig dump key_id TEST=(kohaku) $ ectool --name=cros_fp reboot_ec; sleep 0.5; ectool --name=cros_fp rwsig action abort; sleep 2; ectool --name=cros_fp version | grep "Firmware copy" => Firmware copy: RO TEST=On dragonclaw v0.2 console: rwsiginfo Change-Id: Ib0ee4be33e6636ff702eeaef941cc3abed0594cb Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1999607 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPMv2: Add TypeC functions needed for PD FAFTSam Hurst2020-02-051-0/+47
| | | | | | | | | | | | | | | Add status and control functions that are accessed from the pd console which enables the device to work with PD FAFT. BUG=chromium:1021235 BRANCH=none TEST=make -j buildall Change-Id: I1a33b50646acf0e7036c325eb4cb7a94cc8ec2cd Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962972 Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: move mock header filesJett Rink2020-02-052-0/+44
| | | | | | | | | | | | | | | | Move header files for mocks into the include/mocks folder. These header files aren't just private to the common/mock implementation as the test/ files also need access to these defines. BRANCH=none BUG=none TEST=buildall Change-Id: I25d03d194ab46b7665f54175979577aa90af814f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039038 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* common: queue: Add ability to iterate over queueYuval Peress2020-02-051-0/+28
| | | | | | | | | | | | | | | | | | This is done via: * queue_begin(q) gets an iterator to the start of the list * queue_next(q, &it) updates the iterator to the next element ** Once the iterator reaches the end, ptr will be NULL. ** If the queue was modified between the _begin and _next calls queue_next will terminate the iterator (set the ptr to NULL). BUG=None TEST=New unit tests BRANCH=None Change-Id: I643f544ed91bafac8e8b4c85545d4070f2d82610 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879715 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* TCPMv1: Don't turn off pd module clock if rx enabledRuibin Chang2020-02-051-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Plug in type-c adapter in G3 power state. Because the SLEEP_MASK_USB_PD won't be set before we receive the SRC_Cap from SRC in SNK_Discovery state, but at waiting SRC_Cap this period time we will enter deep sleep mode and turns pd module clock off. This will cause TCPC miss the SRC_Cap message from SRC, then our PD_T_SINK_WAIT_CAP timer timeout and tx hard reset. So I add a configuration: SLEEP_MASK_USB_PD is set only by it83xx driver, so that SLEEP_MASK_USB_PD value won't be overwritten by set_state() function in usb_pd_prtocol.c. If one of the port TCPC Rx is enabled, chip will not go to deep sleep, but chip can go to doze mode that pd module clock won't be turned off only mcu core clock off. if all ports are nothing plug-in, the chip can go to deep sleep. BUG=none BRANCH=none TEST=TCPC doesn't miss any message from partner: -in SNK_DISCOVERY and power G3 state on board ampton. -in SRC_DISCOVERY and power S0 state on board it8xxx2_evb. Change-Id: I9639523e2ca180809f0f74f24321d06e7b3a04c2 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1990935 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* power: Make power_signal_get_level() overridableAseda Aboagye2020-02-051-1/+1
| | | | | | | | | | | | | | | | | This commit makes power_signal_get_level() overridable as there are some boards (like dedede) which have power sequencing inputs which are not simply just GPIOs nor eSPI VW. BUG=b:148169171 BRANCH=None TEST=`make -j buildall` Change-Id: I16fbf54b0688b432c82312a431f1d9f7cc074278 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032727 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Charger: Convert boards to use new driver structureDiana Z2020-02-041-1/+0
| | | | | | | | | | | | | | | This commit removes the temporary common charger chip configuration and instead puts the configuration in each board. BRANCH=none BUG=b:147672225 TEST=builds, runs on waddledoo and octopus Change-Id: If81aef31e48c65999a87e202494f286716114bbb Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031855 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv1/v2: Move dfp_discover_modes() to common fileVijay Hiremath2020-02-041-0/+9
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I83c6dca9652a9c613849b292b4c2329da3f9d424 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032161 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move dfp_consume_modes() to common fileVijay Hiremath2020-02-041-0/+9
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I0a587a68b5c814595d78905f1cdd611f710f2182 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032160 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move dfp_consume_svids() to common fileVijay Hiremath2020-02-041-0/+9
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I3ba96a803fa68d800a3ca41b4ac31e43325c0266 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032159 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move dfp_consume_identity() to common fileVijay Hiremath2020-02-042-7/+9
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I5b0bbd553cbe4fc76478b1c89b0f3f391f074a27 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032158 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move pd_dfp_exit_mode() to common fileVijay Hiremath2020-02-041-0/+8
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: I9d6a219ae031ed9954819c12563867e07bcc8668 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032157 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1/v2: Move pd_dfp_enter_mode() to common fileVijay Hiremath2020-02-041-0/+16
| | | | | | | | | | | BUG=b:148528713 BRANCH=none TEST=make buildall -j Change-Id: Id1d3e8bc27d895a53b53a77cf1c8fd36c69b47dc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032156 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: mag_cal: Trigger online calibration with more samplesGwendal Grignou2020-02-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | For the online calibration to work, sensor data must be collected while the device is in different positions. The current implementation starts calibration after 25 samples/1 second. It means the device should done a figure 8 - or close to it - in that lapse of time. This is fine for phones or small devices, but not for heavy convertible. Increase the batch size to at least 50 samples or 2 seconds of collection. BUG=b:144027014 BRANCH=reef TEST=Pass RVCVXCheckTestActivity verifier test. (cherry picked from commit 2ef4580322d1041c6492ea33058fd4b139d36180) Change-Id: I78d1b943c23eaa9a29831ad4344c8be36ea00b79 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2034677 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* usb_pd TCPMv1: Maintain independent MessageId for SOP''Ayushee2020-02-031-6/+35
| | | | | | | | | | | | | | | | | | | This patchset enables checking and storaging the MessageId counter received from the SOP'' messages. Since SOP*(Cable) communication and SOP(Port Partner) have separate MessageID counters, it is necessary to store separate messageIDs to avoid the the incoming packets from getting dropped. BUG=b:148481858 BRANCH=None TEST=Tested on Volteer, able to maintain separate MessageId count for SOP, SOP' and SOP'' communication. Change-Id: Id3a29594c5f9b354ecb650c6d351b16883d2126b Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032344 Reviewed-by: Keith Short <keithshort@chromium.org>
* Trogdor: Separate the interrupt handlers of WARM_RESET_L and POWER_GOODWai-Hong Tam2020-02-011-1/+9
| | | | | | | | | | | | | | | | | | | | | The original one interrupt handler for two signals will cause a false-postive for the WARM_RESET_L release case, during a transition state that POWER_GOOD goes low but WARM_RESET_L is still high. Use two interrupt handlers for WARM_RESET_L and its pull-up rail POWER_GOOD. It is clear that what signal triggers the interrupt. BRANCH=None BUG=b:148478178 TEST=Called "dut-control warm_reset:on sleep:0.2 warm_reset:off" and saw the message "Long warm reset ended, cold resetting to restore sanity" once. Change-Id: I5a14f91c0dbfacd6a70d01d45f3e8de2b6c6a1cc Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031647 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Tested-by: Alexandru M Stan <amstan@chromium.org>
* TCPMv1: Add support for Thunderbolt active cablesAyushee2020-01-311-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | For entering into Thunderbolt-Compatible mode with active cable, the port sends Enter mode command for SOP', SOP'' (if the cable has a SOP'' controller) and SOP respectively. If the port doesn't receive GoodCRC from Enter Mode SOP'', the port resets the cable characteristic and exits the Thunderbolt-Compatible mode discovery. This CL enables SOP'' communication with the cable plug and adds support to enter into Thunderbolt-compatible mode with active cables. BUG=b:140643923 BRANCH=None TEST=Able to enter into Thunderbolt-Compatible mode for active cables. Change-Id: Iea0c652043933047e0158265c911775d4afe5758 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001938 Reviewed-by: Diana Z <dzigterman@chromium.org>
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