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* pd: Bugfix for write log entry command.stabilize-js-6812.26.Bstabilize-js-6812.25.Bstabilize-js-6812.21.Bstabilize-6812.85.Bstabilize-6812.83.Bstabilize-6812.75.Bstabilize-6812.41.Bstabilize-6812.34.Bstabilize-6812.29.Bstabilize-6812.15.Bstabilize-6812.14.Bstabilize-6812.13.Brelease-R42-6812.BTodd Broch2015-03-031-1/+1
| | | | | | | | | | | | | | | | BRANCH=samus BUG=chrome-os-partner:37264 TEST=manual, ectool --name cros_pd pdsetmode 0 0xff01 1 0 successfully exits displayPort mode again. Change-Id: Ica2faf8de92460f01c2af9be829795c0cd538135 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254990 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 5e9eb3263d4f47f006f7b8e4eeaadd229a8df611) Reviewed-on: https://chromium-review.googlesource.com/255130
* common: Add the possibility to filter UART inputMyles Watson2015-02-212-0/+14
| | | | | | | | | | | | | | | | | | | Add CONFIG_UART_INPUT_FILTER, which is undefined by default. BUG=chrome-os-partner:36745 TEST=buildall for the case where it is not defined. Added a filter function to the btle code on hadoken. Tested reset, transmit test, receive test, test end, and test mode end. BRANCH=None Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I3a9c067ffcb114449b61f468271a48491a8c7ec5 Reviewed-on: https://chromium-review.googlesource.com/250580 Tested-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org>
* cr50: Separate ARM core GPIOs from pinmux configurationBill Richardson2015-02-202-24/+1
| | | | | | | | | | | | | | | | | | | | This separates the configuration of the ARM core GPIOs from the routing of internal peripherals to external pins. Both are still described in the gpio.inc file, but are less dependent on each other. BUG=chrome-os-partner:33818 BRANCH=none TEST=manual Before this CL, running "sysjump rw" or trying to use more than 8 GPIOs caused hangs and reboots. Now it doesn't. Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251015 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: bitmasks should be unsigned valuesBill Richardson2015-02-201-1/+1
| | | | | | | | | | | | | | | Change the struct gpio_info to use uint32_t for the mask field, instead of signed integer. BUG=none BRANCH=none TEST=make buildall Change-Id: I8cc7e3d06a00bd3c890522a896e36e1eb18a862e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251013 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: panic reboot EC if PD MCU crashesAlec Berg2015-02-183-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the EC to check if PD MCU has crashed. The EC knows this by checking the PD status bits: if PD MCU was in RW, and is now in RO, AND it did not get to RO via a sysjump, then it must have crashed. When the EC detects this, the EC will also panic and reboot the entire system, so that we can software sync to a known good state. Also, when EC panics due to PD crash, it will log panic info. BUG=chrome-os-partner:36636 BRANCH=samus TEST=load onto samus EC and PD, try sysjump'ing back and forth on PD MCU console and verify EC does not do anything. Crash the PD MCU when in RW by reboot command and crash divzero command, and make sure the EC panics with PD crash panic message. Crash the PD MCU when in RO (before sysjumping to RW) and make sure EC does not panic. Change-Id: I57961028e6b23a878b8e477a9d8e180cb121a742 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250100 Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cortex-m*: Save panicinfo on non-exception panicsShawn Nematbakhsh2015-02-183-0/+45
| | | | | | | | | | | | | | | | | | Make non-exception "software" panics such as stack overflow and assert failure save a panic log. Log the panic type in r4, and misc. panic data in r5 so that panic reasons can be distinguished. BUG=chrome-os-partner:36744 TEST=Manual on samus_pd. Run 'crash divzero' then 'panicinfo' after reboot. Verify that panic info is printed with "r4 :dead6660". Trigger stack overflow, verify that panic info is printed with "r4 :dead6661". BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5f7a8eb0a5c2ac5799d29bb241deb24fabf38f68 Reviewed-on: https://chromium-review.googlesource.com/249912 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* samus: Only update fan speeds every N secondsBill Richardson2015-02-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This adds CONFIG_FAN_UPDATE_PERIOD to limit the frequency at which the fan speeds are updated. Short version: the CPU core temp fluctuates rapidly, causing the fans turn off and on annoyingly often (assuming you have good hearing and are in a quiet room). With this CL, we limit the speed changes to only once every N seconds. N should be long enough to be less annoying, yet short enough that the CPU doesn't overheat while we're not looking. BUG=chrome-os-partner:34789 BRANCH=ToT,samus TEST=manual Let it sit quietly, then visit a busy webpage, then let it sit a while. The fan speed should only change every 10 seconds or so, not every second. Change-Id: Id985350394f24d56dc4a1e51af09487ac643285b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250501 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* charge_ramp: initial commit of charge ramp moduleAlec Berg2015-02-182-0/+91
| | | | | | | | | | | | | | | | | | | Add new charge_ramp module which works with charge_manager to slowly increase input current limit in order to find the optimal charging current. To do this it looks for either VBUS drooping too low or for the charger to over-current. BUG=chrome-os-partner:34946 BRANCH=samus TEST=tested with a variety of BC1.2 chargers, type-C only chargers, and PD chargers to make sure we always stabilize charging at an appropriate current limit. Change-Id: Icc95aa2738ddb221f163f91c14a342a0674f9e0f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/247304 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* samus: disable i2cscan console command to save spaceAlec Berg2015-02-181-0/+1
| | | | | | | | | | | | | | Disable the i2cscan console command by default to save space BUG=none BRANCH=samus TEST=make -j buildall From .map file, 512 bytes of flash saved Change-Id: I4bcb50b00e843abbc3523a3e0d4cc599a1e01d3a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/249850 Reviewed-by: Vic Yang <victoryang@chromium.org>
* make idlestats console command optionalVincent Palatin2015-02-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | To save flash space, disable "idlestats" console command on samus_pd. This saves 384 B of flash Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:34489 TEST=make buildall and check firmware size. === build/samus_pd/ BASELINE === FLASH 57.8k / 60.0k [ text 48.0k rodat 9.7k data 0.1k ] RAM 11.8k / 16.0k [ data 0.1k bss 11.7k ] === #undef CONFIG_CMD_IDLE_STATS === FLASH 57.4k / 60.0k [ text 47.9k rodat 9.4k data 0.1k ] RAM 11.8k / 16.0k [ data 0.1k bss 11.7k ] Change-Id: Iba9654a88ec195026945881bc2687a1e67747706 Reviewed-on: https://chromium-review.googlesource.com/241452 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* pd_log: Add command to request PD MCU to write a logShawn Nematbakhsh2015-02-122-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we find that charging is in a wedged state, we may wish to write a PD log entry, but the PD MCU cannot detect such a state on its own. Therefore, add a new command to ask the PD MCU to write a log of a given type, and add a new board-specific custom log event. BUG=chrome-os-partner:36668 TEST=Manual on samus: ./ectool --dev=1 pdwritelog charge 0 ./ectool --dev=1 pdwritelog charge 1 ./ectool --dev=1 pdwritelog 1 0 ./ectool --dev=1 pdwritelog 2 0 ./ectool --dev=1 pdlog Verify log output matches expectation: 2015-02-12 11:12:49.290 P0 SRC 2015-02-12 11:12:49.296 P1 SNK Charger PD 20286mV max 20000mV / 3000mA 2015-02-12 11:12:49.303 P0 New connection 2015-02-12 11:12:49.310 P0 Board-custom event --- END OF LOG -- Also, verify kernel logging of wedged event: [ 181.378420] PDLOG 2015/02/12 19:13:44.019 P0 Event 02 (0000) [] Also, trigger wedged state on Samus and verify log entry is written. BRANCH=Samus Change-Id: I55c7c839cf8300fcd3931dccdaaf16c1065e31a8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248981 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cortex-m0: Add deferred schedulerAlexandru M Stan2015-02-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If 2 interrupts happen at the same time, there is a chance that the nested interrupt will not call svc_handler when it needs to. In extreme cases this could lead to tasks not getting woken up when they're supposed to and watchdog resetting. The reason stuff worked was because there were enough other interrupts around to eventually call the scheduler and switch to the ready task. This change modifies the interrupt calls to not call the scheduler directly (because in nested interrupt situation this causes problems), but defer the call to scheduling until after the irq finishes by triggering a low priority interrupt which will for sure call svc_host at the end. The PendSV irq was used for this purpose. BUG=chrome-os-partner:36193 TEST=No more SPI errors caused by scheduler problems TEST=usleeps now are more accurate, they're guaranteed to not take forever now BRANCH=veyron Change-Id: I42acde6b3eb7be2540a0de9a8562dee2ea2be7ab Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248902 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* charge_manager: Minimize log spewShawn Nematbakhsh2015-02-111-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Previously, we tried to minimize log spew by keeping track of previous log entries and not writing new entries in some cases. Instead, we can write a log on the following events only: 1. A port becomes active or 2. A port becomes inactive or 3. The active charge port power limit changes or 4. Any supplier change on an inactive port Also, make charge_manager_save_log a non-static charge manager API function, so that other modules can record a log, if they have reason to believe a port has changed outside of a charge manager change. BUG=chrome-os-partner:33248 TEST=Manual on Samus. Make various power actions and observe logging. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5d5d3e186e85fdb1c59797ffbfb2f5a6ec04d94d Reviewed-on: https://chromium-review.googlesource.com/247891 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* charge_manager: Store dualrole capability in charge managerShawn Nematbakhsh2015-02-112-15/+8
| | | | | | | | | | | | | | | | | | | | Since charge manager is now informed of all capability changes as they happen, it makes sense to store the port capability within charge manager, rather than storing in pd. BUG=chrome-os-partner:36390 TEST=Manual on Samus. Insert 1A Apple charger, verify correct detection. Run 'chgoverride -2' to prevent charging, then repeatedly insert + remove a dual-role charger on the other charge port. Verify that charging is still prevented. Finally, insert a dedicated charger and verify that the override is removed. Also, pass unit tests and verify correct detection in various scenarios with various chargers. BRANCH=Samus Change-Id: I3669050b37ddd67f6608bf790a07e74f86b6ac01 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/247724 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* CCD: Remove CCD specific board connect and disconnectAnton Staaf2015-02-101-13/+0
| | | | | | | | | | | | | | | | | | | | Previously the Case Closed Debugging system provided a way for the board to connect and disconnect the CCD USB lines correctly, but this functionality is better implemented by board_set_usb_mux. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I697ee9740c64ac93557d9fca8b2d10e858c51193 Reviewed-on: https://chromium-review.googlesource.com/247721 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Power Button: Wait for power button to be stable when waiting for releaseAlexandru M Stan2015-02-101-0/+9
| | | | | | | | | | | | | | | | | | The debounce timer might be too slow to actually update the state of debounced_power_pressed by the time we do power_button_is_pressed in the S3->S5 state transition. Solution is to move the power_button_wait_for_release function here and make sure there are no deferreds active. BUG=chrome-os-partner:35948 TEST=During dev mode screen, press power button, note the device stays off TEST=Print debounced_power_pressed in power_button_is_pressed(void), note it's not 0 when power button is actually pressed BRANCH=veyron Change-Id: I8258e9e5524bd65d6ea9c77ea5649304d2195bf0 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/244590 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-1/+16
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* charge_manager: Wait for dualrole determination before chargingShawn Nematbakhsh2015-02-082-4/+14
| | | | | | | | | | | | | | | | | | | | | | | If a dual-role charger is plugged, we will not realize it is dual-role until after we see a type-C charge source. It can cause us to briefly charge from a dual-role charger, which has bad side effects related to charge override and the lightbar. Fix this by not charging from a port until we are fairly certain that it is a dedicated charger (based upon PD discovery timeout). BUG=chrome-os-partner:36390 TEST=Manual on Samus. Insert 1A Apple charger, verify correct detection. Run 'chgoverride -2' to prevent charging, then repeatedly insert + remove a dual-role charger on the other charge port. Verify that charging is still prevented. Finally, insert a dedicated charger and verify that the override is removed. Also, pass unit tests and verify correct detection in various scenarios with various chargers. BRANCH=Samus Change-Id: Ia4154f34dd0a850b6e72bebadbd938f034532f14 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/247130 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Support vboot hash and system version if flash isn't memory-mappedRandall Spangler2015-02-052-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some EC chips (mec1322) use external SPI flash which is not mapped into the EC CPU's address space. These must explicitly read data from flash when calculating the vboot hash or reading the version string of the image which isn't currently loaded into code RAM. To test this bug, I used a board with known working mapped flash, and temporarily patched it to act like it didn't have mapped flash. Also add a flashread console command, useful for manually testing. BUG=chrome-os-partner:35308 BRANCH=glower,strago TEST=manual 1. Apply this patch to samus 2. Check result for 'vboot hash RW' 3. Check result for 'version' 4a. In board/samus/board.h, #undef CONFIG_FLASH_MAPPED and #define CONFIG_CMD_FLASH 4b. In chip/lm4/flash.c, add the following: int flash_physical_read(int offset, int size, char *data) { const char *src; if (offset > CONFIG_FLASH_SIZE || offset + size > CONFIG_FLASH_SIZE) return EC_ERROR_INVAL; src = (const char *)((uintptr_t)CONFIG_FLASH_BASE + offset); memcpy(data, src, size); return EC_SUCCESS; } Steps 4a,4b will make the LM4 chip act like it doesn't have memory-mapped flash. 5. From the dev system, util/flash_ec --board=samus --ro 6. Check result for 'vboot hash RW'. Should be same as 2. 7. Check result for 'version' for RW version. Should be same as in 3. 8. From the dev system, util/flash_ec --board=samus 9. sysjump rw 10. Check result for 'version' for RO version. Should be same as in 3. 11. Compare 'flashread 0x100 0x100' with 'md 0x100 0x40'. The results should be the same (but endian-swapped, since flashread is byte ordered and md is 32-bit ordered). 12. Revert changes from steps 4a-4b. Change-Id: I951d6f5603a84e326740936e4e84dfe6296a0f59 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/246200 Reviewed-by: Shawn N <shawnn@chromium.org>
* Convert motion sense calculations to fixed point.Randall Spangler2015-02-053-20/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Motion sense calculations do not require huge amounts of precision, so fixed point is plenty accurate. And fixed point works on Cortex-M0, which lacks a FPU. BUG=chrome-os-partner:36126 BRANCH=minnie (samus already works with the FPU, but could grab this if we want additional testing) TEST=manual 1. Boot system 2. At EC console: accelinfo on 250 3. Move lid through several different angles (30 degrees to max open) and see that it updates correctly and relatively smoothly. A few degrees of angle jitter is normal. 4. At several angles, rotate the chromebook around and see that the lid angle remains relatively stable. 5. If the hinge is made normal to the ground (or within 15 degrees of vertical), the angle should read 500, since the acceleration vectors don't yield good results in that orientation (for either fixed or float math). And run 'make buildall -j', which tests arc_cos() and lid angle calculations Change-Id: I70a0d08b8914629a3e21ae5578cbe8e50f29ad68 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/244116 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* samus: fix lightbar tap sequence doesn't always show on AC eventAlec Berg2015-02-041-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | Fix bug on samus that the battery status doesn't always show on lightbar when AC is plugged/unplugged. It doesn't show when the battery is full is S3 or S5 because in these states we turn off CHARGE_EN so that ACOK to the EC never toggles. Instead, what we want to do is display battery status whenever the active charge port changes. This will happen when AC is plugged or unplugged OR if a user has AC on both ports and toggles between them using the charge override hot-keys. BUG=chrome-os-partner:36317 BRANCH=samus TEST=test plugging and unplugging AC on both sides when battery is full and unit is in S0, and when unit is in S5. also tested lightbar flashes battery percentage when two zingers are plugged in and you switch between them using Ctrl+Search+0|1|2. Change-Id: I5cd7fff4f466adf857f1e63f07f3b0c7ae8422c7 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/245922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: automatically recover from charge circuit failuresstabilize-6752.BAlec Berg2015-02-034-8/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Occasionally the charge circuit on samus gets wedged and will not charge. This change detects when the charge circuit has failed and automatically recovers from it. It uses the BQ PROCHOT warning to detect the failure by setting PROCHOT to trigger when the BQ thinks input current is higher than the input current limit. When the failure is detected, the EC disables charging and tells PD MCU to disable CHARGE_EN, then a couple seconds later, it re-enables charging. This CL also adds more communication between EC and PD for the EC to be able to set the charge state for the PD. Valid charge states are: No charging allowed, 5V charging only, and max charging. The EC uses this as such: - When the EC gets AC present interrupt, it sets off a deferred function to change charge state to max charging after some delay to give time for the charge circuit to settle down. - When the EC gets AC disconnect interrupt, it disables charging briefly, enables learn mode, and then sets 5V charging allowed. This allows for the same starting conditions in the charge circuit for every AC attach. - When the EC detects a wedged charge circuit, it disables charging and waits a few seconds before re-enabling 5V only charging. Additionally, this change moves the charging cutoff in S3/S5/G3 when the battery is full to the EC. With the added control for the EC to set the PD charging state, it is more convenient for the EC to manage cutting off charging when battery is full. BUG=chrome-os-partner:36081 BRANCH=samus TEST=test the basics: - connect/disconnect zinger a bunch of times - connect and disconnect two zingers in different order - connect two zingers and charge override between the two test the automatic charge wedge recover: - wedge the charge circuit by setting charger voltage under battery voltage: "charger voltage 7000" - wait a few seconds for the system to recover and check it is charging with "battery" command test full battery charge cutoff: - added console command to change battery soc in board/samus/extpower.c: static int cmd_battfake(int argc, char **argv) { char *e; battery_soc = strtoi(argv[1], &e, 10); batt_soc_change(); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(battfake, cmd_battfake, "", "", NULL); - in S0, tested "battfake 100" does not disable charging. - in G3, tested "battfake 100" disables charging and "battfake 99" re-enables charging. - set "battfake 100" and tested transitioning to S0 enables charging and transitioning to S5 disables charging. - attached two chargers and used charge override to select active port. then toggled "battfake 100" to "battfake 99" back and forth and verified charge override port is still the same. test third-party 12V charger: - plug in a bunch of times and make sure we stay at 5V for 500ms and then transition to 12V test with no battery: - tested five different units with no battery and just zinger. 3/5 boot, while the other 2 don't. But, the 2 that don't boot without battery also can't boot w/o battery when this CL is reverted, so I don't think this change is causing the problem, I think there is an electrical limitation. test with EVT zinger: - EVT zingers (P2 - C2) negotiate very quickly after connection, which can cause INA problems w/o this CL. Tested an EVT zinger with samus and did a bunch of connections and disconnections and verified that we always wait at 5V for 500ms and that we don't wedge the INA circuit on connect. test backwards compatibility: - test new PD with old EC and make sure we can charge with zinger. (note that if the charge circuit wedges, we won't be able to unwedge it). - test old PD with new EC and make sure we can charge with zinger. Change-Id: I7703b7a2ab1209d7f559b265b03517e79c74b16a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/245253 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* hooks: add hook for battery state of charge changeAlec Berg2015-02-032-0/+9
| | | | | | | | | | | | | | Add hook for battery state of charge change. Hook will be used to cleanup the samus charging workarounds to follow. BUG=none BRANCH=samus TEST=make -j buildall Change-Id: I99cbb8264783802139cac689804b056623063695 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/245252 Reviewed-by: Shawn N <shawnn@chromium.org>
* mcdp28x0: Move structure definitions to ec_commands.hShawn Nematbakhsh2015-01-311-0/+20
| | | | | | | | | | | | | | mcdp_info is a logging payload, so related structures need to be moved to the public include file. BUG=chrome-os-partner:35935 TEST=make buildall -j BRANCH=Samus Change-Id: Idb939db884821fa85faafbfe643e713f5bcdbc59 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/244780 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: Log events for dingdong & hohoTodd Broch2015-01-281-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:35935 TEST=manual, see new events for dingdong & hoho. Note must be in GFU mode to facilitate. Change-Id: I1b79237512748796cf98765a553af8c9978cb594 Reviewed-on: https://chromium-review.googlesource.com/243374 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org>
* pd: Allow multiple mode entry.Todd Broch2015-01-282-12/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current simplified implementation allows single mode entry. Specification allows multiple mode entry and its advantageous for things like flashing RW while staying in DisplayPort mode on video dongles. CL adds capability on DFP to track as many alternate modes as supported by the DFP. Initial mode entered is still the default supported mode ( 1st entry, 1st opos). Policy manager can then use host command, EC_CMD_USB_PD_SET_AMODE, to enter additional supported modes. On the UFP (hoho, dingdong) a small modification to track multiple svid mode entries was made. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:33946 TEST=manual, On hoho 1. Still successfully enter default mode DP 2. Using ectool's pdsetmode can successfully enter/exit multiple modes. For example, # port:1 svid:18d1 opos:1 cmd:1==enter ectool --name cros_pd pdsetmode 1 0x18d1 1 1 Checking with pdgetmode shows both modes entered. 3. Works across hard & soft resets 4. Can flash via ectool --name cros_pd flashpd 4 <port> <RW image> 5. Still drives external display. With bootarg drm.debug=0x6 and following command: 'tail -f /var/log/messages | grep "Received HPD" &' I see HPD assert & deassert when switching between GFU and DP mode. If both modes entered screen stays lit (after reboot) during write. Change-Id: I7a21ebea377402eb1b0a0cf1d29df59694e301b1 Reviewed-on: https://chromium-review.googlesource.com/241790 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org>
* pd: refactor object position index.Todd Broch2015-01-282-2/+5
| | | | | | | | | | | | | | | | | | | | | | Renaming this to 'opos' for consistency with USP-PD specifications 'object position' in VDM header. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:35495 TEST=manual, On hoho 1. Still successfully enter default mode DP 2. Using ectool's pdgetmode pdsetmode can successfully enter/exit other modes 3. Works across hard & soft resets Change-Id: I08cb8e003ced4de481adcb503bcba3437ebb1ab7 Reviewed-on: https://chromium-review.googlesource.com/241718 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org>
* samus: change charge override hot keys to ctrl+search+0|1|2Alec Berg2015-01-241-3/+9
| | | | | | | | | | | | | | Change the charge override hot keys to ctrol+search+0|1|2 BUG=none BRANCH=samus TEST=use the hot keys and verify that the PD console shows charge override host command Change-Id: I5551190743ea064a967164b9d95143cc966662e1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/242832 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: poll PD events only on Google accessoriesVincent Palatin2015-01-241-0/+8
| | | | | | | | | | | | | | | | | | | | Poll USB PD accessories for event log entries only after we have performed a Discover Identity and identified them as a Google device (USB VID = 0x18d1) in order to avoid confusing third party devices with our logging VDM. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:35858 TEST=connect Zinger to Samus and see the proper PD log entries. Change-Id: I022fa0d19dc012e46a27b786a724ff251280eeaf Reviewed-on: https://chromium-review.googlesource.com/242871 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: retrieve logs from accessoriesVincent Palatin2015-01-211-0/+17
| | | | | | | | | | | | | | | | | Send the VDO_CMD_GET_LOG VDM to accessories to get their PD event log and append it to the PD MCU log. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:33248 chrome-os-partner:32785 TEST=ectool --name=cros_pd pdlog Change-Id: Ib52d1e2cae5f77dcec6d0489eaa49527388b02b6 Reviewed-on: https://chromium-review.googlesource.com/242013 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* pd: export the data role to the APVincent Palatin2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | For dual-role USB ports (host/device), let the AP know whether we are currently DFP (USB host) or UFP (USB device) by exporting the data role in addition to the power role in the EC_CMD_USB_PD_CONTROL response. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=none TEST=ectool --name=cros_pd usbpd 0 plug various accessories on the port and see properly "SRC DFP" for the USB key, "SNK DFP" for the power supply and "SNK UFP" for a regular C-to-A charging cable. Change-Id: I292da15fa8cf3566109dd05995ef1d00bed6f92d Reviewed-on: https://chromium-review.googlesource.com/242012 Reviewed-by: Alec Berg <alecaberg@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* samus: Add scale factor to account for ALS attenuationBill Richardson2015-01-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds a sensor-specific attentuation factor, which will be applied to the ALS raw sensor readings on the EC. This is to account for the attenutation due to glass, tinting, etc. BUG=chrome-os-partner:34590 BRANCH=ToT,Samus TEST=manual In a root shell, run this: cd /sys/bus/acpi/drivers/acpi_als/ACPI0008:00/iio:device1 while true; do cat in_illuminance_raw; sleep 1 ;done Shine a flashlight on the ALS. Note that the readings are 5X higher than they were before this CL. Change-Id: I2a53872ecb5fab62e5f443d43588a26d3d7e697f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241191 Reviewed-by: Bryan Freed <bfreed@chromium.org>
* Strago: emerge-strago build error fixedDivya Jyothi2015-01-201-0/+1
| | | | | | | | | | | TEST=None BUG=None BRANCH=None Change-Id: Ib4c42264f105ac96558e4a03f22f9b71b2781c11 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/240930 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Initial Glower commitVic Yang2015-01-201-0/+4
| | | | | | | | | | | | | | | The first commit for the Glower board. BRANCH=None BUG=chrome-os-partner:35308 TEST=Boot on Glower and check console is responsive. Change-Id: I73bc60b8d54b3c570f0822824ad9a66e0fe467a1 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/239257 Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* pd: samus: do not request voltage within boost bypass deadbandAlec Berg2015-01-171-0/+8
| | | | | | | | | | | | | | | | | Do not request a voltage that is within the deadband where we aren't sure if the boost or the boost bypass is on. BUG=chrome-os-partner:34938 BRANCH=samus TEST=test on samus with zinger. change the deadband to [10V, 20V] and see that we only negotiate to 5V. change the deadband to [13V, 20V] and see that we negotiate to 12V. change the deadband to [10V, 13V] and see that we negotiate to 20V. Change-Id: Id761aef35eeadfa2ab7d2ca31a48d4324625ab32 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241528 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus_pd: Don't re-request FW update if RW is already the latestShawn Nematbakhsh2015-01-171-2/+4
| | | | | | | | | | | | | | | | | | The AP informs us of the latest update image for a given device through the EC_CMD_USB_PD_RW_HASH_ENTRY command. If the latest update image is equivalent to our RW, we don't need to request an update. BUG=chrome-os-partner:35510 TEST=Manual on Samus. Flash latest RW FW to Zinger. Verify that subsequent Zinger insertion doesn't trigger the FW update host event. Insert RO-stuck Zinger and verify that FW update host event is triggered. BRANCH=Samus Change-Id: I300b150b3469e3fe32307e61273880a1a052ac5a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241172 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* I2C: Increase priority of i2c_initAlexandru M Stan2015-01-161-5/+7
| | | | | | | | | | | | | | | | Chipset sometimes needs I2C, therefore i2c_init should have a higher priority than power_common_init so i2c is available by the time the chipset might be talking to the battery. BUG=chrome-os-partner:35502, chrome-os-partner:35173 TEST=There is no "battery not responding" message at startup on veyron TEST=EC boot takes less than 1 second on veyron BRANCH=none Change-Id: Ib10b653decc7703e706d4dd1976abf0fdbc25ac2 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241102 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: updates to new connection state machineAlec Berg2015-01-162-2/+3
| | | | | | | | | | | | | | | | More updates to connection state machine. Adds CONFIG option for backwards compatible DFP (used on zinger), and change UFP state machine to debounce CC while VBUS is not present. BUG=chrome-os-partner:33680 BRANCH=samus TEST=load on samus and zinger and connect a bunch of times. also test samus to samus connection. Change-Id: Ia967eb6a17b10aa0c05a30686235fbf8a24e9a7b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240587 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add USB-PD mode commands.Todd Broch2015-01-161-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These commands (pdgetmode & pdsetmode) will provide host with ability to identify USB-PD alternate mode devices SVIDs and supported modes. It will also allow host to set mode on devices which support multiple alternate modes. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:33946 TEST=manual Plug hoho/dingdong into samus at port <port> ectool --name cros_pd pdgetmode <port> *SVID:0xff01 *0x00001085 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 SVID:0x18d1 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ectool --name cros_pd pdsetmode <port> 0x18d1 1 ectool --name cros_pd pdgetmode <port> SVID:0xff01 0x00001085 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 *SVID:0x18d1 *0x00000001 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 ectool --name cros_pd infopddev <port> Port:1 DevId:4.1 Hash: 0x042cc79c 0x30cc12e3 0xe27a36e5 0x3f7eba5f 0x053c91d1 Port:1 ptype:5 vid:0x18d1 pid:0x5010 Also from samus_pd console see proper result for 'typec <port>' typec 1 Port C1: CC1 178 mV CC2 427 mV (polarity:CC2) No Superspeed connection Also visually inspect packets via twinkie. Change-Id: I4e442bcb39ec1ff3cb6efff196a660819077ad76 Reviewed-on: https://chromium-review.googlesource.com/231834 Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: Remove rwhashtable dumping by default for flash space.Todd Broch2015-01-161-0/+1
| | | | | | | | | | | | | Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:34489 TEST=compiles, saves ~200bytes Change-Id: I72493618af0884936c8e634fa7d52b7ecc4ab4a4 Reviewed-on: https://chromium-review.googlesource.com/241019 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org>
* charger: Make critical battery shutdown timeout a config optionShawn Nematbakhsh2015-01-152-3/+12
| | | | | | | | | | | | | | | | Certain platforms may wish to have a longer shutdown timeout, so make the timeout a config option. BUG=chrome-os-partner:35188 TEST=Manual on Samus with subsequent CL. Set config option to increase timeout, verify that timeout is extended. BRANCH=Samus Change-Id: I69feb0d31fdc53e533671dec1e88ba96cc4553c2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240815 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: log important events for accessoriesVincent Palatin2015-01-151-3/+9
| | | | | | | | | | | | | | | | | | | Record in the PD log when we fail to verify the RW signature and when the RW partition is erased. Also log the faults on the power supplies. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:32785 TEST=flash a bad rw on Zinger. Change-Id: Ib62dcb0d407867151af0aaecc405533e894d773e Reviewed-on: https://chromium-review.googlesource.com/239913 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add PD events loggingVincent Palatin2015-01-153-3/+107
| | | | | | | | | | | | | | | | | | | | | | Add a FIFO to log important events on the PD MCU and coming from the PD accessories. The retrieval of the accessories log from the accessories by the PD MCU is not implemented yet. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:32785 TEST=execute "ectool --name=cros_pd pdlog" before and after plugging Zinger charger. Change-Id: If96d73e711ff6ad64cfb99bd3e4d2d8f2643f19a Reviewed-on: https://chromium-review.googlesource.com/238854 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* zinger: remove functions for analyzing bist resultsAlec Berg2015-01-141-0/+2
| | | | | | | | | | | | | | | | | Remove functions for sending bist command and analyzing the resulting stream in order to save flash space. BUG=chrome-os-partner:32785 BRANCH=samus TEST=make -j buildall Change-Id: I8fec2d632bce82b1cc344e674b48c5cf2b3a3647 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240700 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Standard Power/Charging LED BehaviorAlexandru M Stan2015-01-141-0/+12
| | | | | | | | | | | | | | | | | | | | | Assuming the dut has red/green battery led and a single power led CONFIG_LED_POLICY_STD implements the chromeos spec: * power led on in S0 * power led off in S5 * power led pulsing in S3 * battery led amber when charging * battery led green when fully charged with AC * battery led off when discharging * battery led pulsing red when battery error BUG=chrome-os-partner:35355 TEST=The Charging led behavior should match the cros spec BRANCH=None Change-Id: I645a939ecc2d44d73d2f52b295f9c7e8c923f77b Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240705 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: increase tCCDebounce to 100msAlec Berg2015-01-141-1/+1
| | | | | | | | | | | | | Increase CC debounce time to the spec 100ms. BUG=chrome-os-partner:33680 BRANCH=samus TEST=load onto samus and zinger and connect. Change-Id: If4b9d4d50540c241c462f461a09371d2fffa6621 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240586 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Add a forcetime console commandMyles Watson2015-01-141-0/+1
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:35312 BRANCH=none TEST=make buildall -j I added a debug message to nrf51/hwtimer.c to show when the timer overflowed. "forcetime 4 0xfffff000" overflows to 5.00000000 in 4096 microseconds. Define CONFIG_CMD_FORCETIME to enable it. Change-Id: I30835d038ef8cd639565ffb7a638979d95d0a684 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/239968 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-141-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
* Show the fan-cooling percentage for each active temp sensorBill Richardson2015-01-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When displaying the temps, if the sensor has valid entries to control the target fan speed, show them. This lets us see which sensor is the main player in the cooling needed without doing a bunch of math. BUG=none BRANCH=none TEST=manual On the EC console: > thermalget sensor warn high halt fan_off fan_max name 0 368 370 372 316 358 PECI 1 0 0 0 0 0 ECInternal 2 0 0 0 314 328 I2C-Charger-Die 3 0 0 0 0 0 I2C-Charger-Object 4 0 0 0 308 322 I2C-CPU-Die 5 0 0 0 0 0 I2C-CPU-Object 6 0 0 0 301 317 I2C-Left C-Die 7 0 0 0 0 0 I2C-Left C-Object 8 0 0 0 302 316 I2C-Right C-Die 9 0 0 0 0 0 I2C-Right C-Object 10 0 0 0 303 317 I2C-Right D-Die 11 0 0 0 0 0 I2C-Right D-Object 12 0 0 0 316 327 I2C-Left D-Die 13 0 0 0 0 0 I2C-Left D-Object Then, before this CL: > temps PECI : 308 K = 35 C ECInternal : 309 K = 36 C I2C-Charger-Die : 307 K = 34 C I2C-Charger-Object : Not calibrated I2C-CPU-Die : 304 K = 31 C I2C-CPU-Object : Not calibrated I2C-Left C-Die : 302 K = 29 C I2C-Left C-Object : Not calibrated I2C-Right C-Die : 303 K = 30 C I2C-Right C-Object : Not calibrated I2C-Right D-Die : 303 K = 30 C I2C-Right D-Object : Not calibrated I2C-Left D-Die : 306 K = 33 C I2C-Left D-Object : Not calibrated After this CL: > temps PECI : 308 K = 35 C 0% ECInternal : 309 K = 36 C I2C-Charger-Die : 307 K = 34 C 0% I2C-Charger-Object : Not calibrated I2C-CPU-Die : 304 K = 31 C 0% I2C-CPU-Object : Not calibrated I2C-Left C-Die : 302 K = 29 C 6% I2C-Left C-Object : Not calibrated I2C-Right C-Die : 303 K = 30 C 7% I2C-Right C-Object : Not calibrated I2C-Right D-Die : 303 K = 30 C 0% I2C-Right D-Object : Not calibrated I2C-Left D-Die : 306 K = 33 C 0% I2C-Left D-Object : Not calibrated Change-Id: I12bca5826e8a5a3325710fa5d39cec88f1cc95b1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240517
* charger v2: Combine prevent_*_discharge functionsShawn Nematbakhsh2015-01-131-2/+1
| | | | | | | | | | | | | | | | prevent_hot_discharge and prevent_deep_discharge are near-identical copies of one another, and can be combined without the loss of any useful functionality. BUG=chrome-os-partner:35188 TEST=Manual on Samus. Charge to 2% and boot system with 5V power supply. Verify that warnings print to console and AP powers down after 30s. Also pass unit tests. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0f1da5248825a3884f7910babc742dfa7eadf5a3 Reviewed-on: https://chromium-review.googlesource.com/240033
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