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* Check for recovery key sequence at initRandall Spangler2012-02-141-1/+4
| | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7451 TEST=hold down no keys; KB init state should be blank hold down reload (F3); KB init should indicate recovery key pressed hold down F3 + ESC; same hold down F3 + F2 + ESC; KB init should NOT indicate recovery key pressed Change-Id: I0fbf15407b20669396f667e6499ee5a9d545a4d5
* Add 8-bit I2C read/write functions.Bill Richardson2012-02-131-0/+10
| | | | | | | | | | | | These provide 8-bit accesses to registers within an I2C device. BUG=chrome-os-partner:7839 TEST=none Testing will come when I start using them. Change-Id: Ib53d3347253bccee93cb9c5da12db92970155d92 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Fix discovery and bds builds, which don't have temp sensor or peciRandall Spangler2012-02-132-2/+4
| | | | | | | | | | | | | Remove id field from temp_sensor_t struct, since it's only used by the console command (which already knows the id, because it's looping over it). Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='temps' Change-Id: I0970850073d644509cd5501d7ac4421c7373143b
* Add basic smart battery driverRong Chang2012-02-102-2/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a common part of smart battery driver. Following features are not implemented, or in chip specific driver: Battery access control, authentication, factory mode Manufacturer access/data commands Block read/write, device name, flash data Chip specific features, per cell info/temp/capacity Signed-off-by: Rong Chang <rongchang@google.com> BUG=chrome-os-partner:7856 TEST=console command check battery staus [unplug power] > battery [check voltage,current,capacity,time to empty] [plug power] > charger voltage 8400 > charger current 4250 > battery [check current,time to full] > charger input 4032 > battery [check current,time to full] [wait 130 seconds, charger watch dog timeout] > battery [check current] Change-Id: Ifac17a0892f52e8f37eebc14b00e71f18360776c Signed-off-by: Rong Chang <rongchang@chromium.org>
* Add PECI module and CPU temperature monitoringRandall Spangler2012-02-101-0/+28
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7493 TEST='powerbtn' to boot main processor, then 'temps' and 'pecitemp' Change-Id: Id57526ebb37c8aecb05ecebccc2824f462b9de1a
* Send scan code to host when power button is pressed/released.Louis Yung-Chieh Lo2012-02-102-0/+9
| | | | | | | | | But only if the system is in S0. Approved at internal gerrit: 11595. BUG=none TEST=tested on bds.
* Merge "Add tmp006 object temperature calculation"chrome-bot2012-02-081-2/+5
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| * Add tmp006 object temperature calculationVic Yang2012-02-081-2/+5
| | | | | | | | | | | | | | | | | | | | Implement TMP006 object temperature calculation. Also add a console command to calculate temperature with manually entered data. BUG=chrome-os-partner:7801 TEST=In console, "tempremote 29715 -105000 6390" gives 285.00K. Change-Id: I0f9193fb970fdc36566399e7083e73ab58965a85
* | Merge "Initial bq24725 charger driver import"chrome-bot2012-02-071-0/+44
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| * | Initial bq24725 charger driver importRong Chang2012-02-071-0/+44
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery charging state machine contains many file changes. This is the 1st part of the break down. Refactor original test code into board dummy driver. Normalize charger API. And import link's charger IC driver. Signed-off-by: Rong Chang <rongchang@google.com> BUG=chrome-os-partner:7855 TEST=build without warning and error BOARD=bds make BOARD=link make BOARD=discovery make Change-Id: I34b6e9862a45331378916bc77653d4adb22ca548
* | Handle up/down arrow keys for UART console.Vic Yang2012-02-071-0/+1
|/ | | | | | | | | | | | | | | | | | | | | | Record commands used previously and use up/down arrow key to navigate in the command history. Also removed the command '.' of repeating last command as we can use up arrow key now. Also changed the behaviour of uart_write_char() to be blocking on transmit FIFO full, so that we do not lose echoed character and do not need to flush. BUG=chrome-os-partner:7815 TEST=Type 'help' and enter. Then type 'aaaa' and up arrow key, should show 'help', and pressing enter prints help. Type 'hellp' and enter. Then type 'aaaaaa' and up arrow key, should show 'hellp'. Should be able to use left/right arrow key and backspace to correct it to 'help', and pressing enter prints help. Type 'help' and enter. Then type 'aaa', up arrow key, and down arrow key. Should show 'aaa'. Change-Id: I65c615d61bf63acb31bea329aa91a3202d4db0ad
* Merge "Additional compilation fix-ups for non-LM4 targets"chrome-bot2012-02-061-3/+0
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| * Additional compilation fix-ups for non-LM4 targetsDavid Hendricks2012-02-061-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add #ifdef CONFIG_TEMP_SENSOR before #include'ing temp_sensor.h which actually requires temp_sensor_id to be defined. Revert the forward declare used earlier since it is not the correct solution in this case. - Add #ifdef CONFIG_CHARGER before calling charger_init() Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=None TEST=compiled on both BDS and Discovery Change-Id: I60b7e4ba91eb958b3ad724cc9ffa9a12fe9c3a71
* | Merge "Add UART1 receive support (UART to x86 console)"Randall Spangler2012-02-062-1/+4
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| * Add UART1 receive support (UART to x86 console)Randall Spangler2012-02-062-1/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7488 TEST=type things into the x86 console UART; should appear on the u-boot prompt Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
* | Add forward declarations in ADC and temp_sensor headersDavid Hendricks2012-02-062-0/+6
|/ | | | | | | | | | | | This is a trivial patch to fix compilation for boards that are not based on LM4 (e.g. Discovery). Signed-off-by: David Hendricks <dhendrix@chromium.org> TEST=Compiled for Discovery BUG=None Change-Id: Ia1f29c61ff4a1f65fe65c43a8e58def7d1217ab2
* Refactor temperature sensor code and add support of Link I2C temp sensor.Vic Yang2012-02-043-4/+68
| | | | | | | | | | | | Refactor board/chip-specific code into corresponding directories. Add support of the four I2C temp sensor in Link. Use table lookup to handle different types of temperature sensors. BUG=chrome-os-partner:7527 TEST=Correctly read EC internal temperature on bds. Compile for link succeeded. Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
* Merge "Fix the missing IRQ problem."Louis Yung-Chieh Lo2012-02-022-0/+26
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| * Fix the missing IRQ problem.Louis Yung-Chieh Lo2012-02-022-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem comes from the different assumption of interrupt mode in EC and the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge. However, the auto-IRQ functino of EC is level-triggered and uses low-active to assert an IRQ. This makes the deadlock so that the kernel never gets an interrupt until a byte is manually pulled from host. So, the solution is manually firing an IRQ_1 to host after EC puts a byte to port 0x60. Note that the auto IRQ needs to be disabled in order to avoid the interference with manual IRQ generation. This CL also moves chip specific code to lm4/lpc.c and handle some minor keyboard commands. BUG=none TEST=on hacked baord. Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
* | Fix a bug that ADC input is not correctly configured.Vic Yang2012-02-021-0/+1
|/ | | | | | | | | | The ADC input pin was always configured as BDS. Modified it to configure the correct pin. BUG=none TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7. Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
* Merge "Refactor ADC code and add Link charger current ADC support"chrome-bot2012-02-011-17/+14
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| * Refactor ADC code and add Link charger current ADC supportVic Yang2012-02-021-17/+14
| | | | | | | | | | | | | | | | | | | | | | Refactor ADC code and move board/chip-specific part to corresponding directories. Implement function and console command to read Link charger current. BUG=chrome-os-partner:7527 TEST=Read EC temperature and POT input on BDS. Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
* | stm32l: add UART driverVincent Palatin2012-01-311-0/+6
|/ | | | | | | | | | | | simple UART driver to get the serial console on the USART3. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on Discovery board and check we get the first message on the UART and the console is echoing the characters. Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
* expand properly the IRQ number for IRQ declaration macroVincent Palatin2012-01-301-1/+1
| | | | | | | | | | | | Expand the macros before building the priority variable name in order to ensure we have a valid name. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=check manually preprocessor expansion for several combinations. Change-Id: I926821d42c966ac674e7d24254c9f22779f93ca2
* Eat terminal escape sequencesRandall Spangler2012-01-271-0/+1
| | | | | | | | | | | | | I keep hitting the darn arrow keys. Until we can do something more elegant like a real command history, this will at least keep me from corrupting the display and input buffer. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=type 'help' and some arrow keys, then enter. Should print help, not an error. Change-Id: Idb552e9c22876fc2dc1f349f0038e94048f00aa7
* Split reset cause and image copy code.Vincent Palatin2012-01-261-0/+3
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 3rd series 2/2 All the RO/A/B firmware copy code could be generic to all our platforms. The console commands are a 'standard' API. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on BDS EC console, check the reset cause with the 'sysinfo' command. Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
* Split UART codeVincent Palatin2012-01-261-0/+60
| | | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 3rd series 1/2 Most of the code is handling the buffering and the printf, thus put it in an hardware independant location and only implement the UART dependant portions in the chip driver. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on BDS and stress the console. Change-Id: I9376f2fa1dad341eac808e1756dbeff32900bd51
* Move SoC-independant headers to another directoryVincent Palatin2012-01-261-0/+21
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 1/4 The atomic operations are SoC independant since they are only using LDREX/STREX instructions which are just core specific ARMv7-M). The watchdog header defines the API which is common to all platforms. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands
* Split the timer code between OS code and hardware dependant code.Vincent Palatin2012-01-251-0/+43
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2/5 The hwtimer.* files implement the driver for the SoC timer block. The timer.* files provides the OS level clock/timer functions. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on BDS, check 'waitms' and 'gettime' on the EC console. Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
* Go back to SoC independant IRQ vectors declarationVincent Palatin2012-01-251-6/+5
| | | | | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 1/5 Instead of putting hardcoded IRQ SoC name in the vector table, upgrade the DECLARE_IRQ macro to expand its argument. Also add a parameter to set the size of the NVIC table to save flash memory. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC on BDS and see timer IRQs firing. Change-Id: I44fefdabdd37d756492a71f24554979c72c1b50f
* Initial mutex implementationVincent Palatin2012-01-252-0/+16
| | | | | | | | | | | | | | | | | | | They are designed to protect shared hardware resources (e.g. I2C controller). Please refrain using them as a general purpose synchronization primitive for the tasks to avoid unintended slippery effects (e.g. priority inversion), use the provided message-passing functions instead for that purpose. The mutex variable (ie the "struct mutex") should be initially filled with 0, but this is the default compiler behavior if you declare it as a global variable. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make qemu-tests Change-Id: I328f7eadf5257560944dbbbeda0b99d5b24520e8
* register console commands at compile-timeVincent Palatin2012-01-241-11/+6
| | | | | | | | | | | | | | | Instead of using a runtime callback to register the console commands, put them in a special linker section. So we can do a macro to "register" them during the build. It saves 684 bytes and a few microseconds at startup. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run a few commands from the BDS command line. Change-Id: Id33ea210b9035bf76ed720373c74c5dd24ccd1b1
* USB Charging controlVic Yang2012-01-191-0/+34
| | | | | | | | | | | | | | Implement TPS2543 USB charging control. It contains routine for setting each USB port as dedicated charging port or standard downstream port. To allow us controlling the current distributed to each port, we can select whether to allow 500mA or 1500mA for each port. BUG=chrome-os-partner:7476 TEST=Added USB port definition for BDS and tested GPIO output voltage level is correct for all modes. Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
* Handle all GPIO IRQs. Interrupts no longer enabled by default.Randall Spangler2012-01-171-3/+3
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7456 TEST=if it runs, it works Change-Id: Ib82afab7d53203af31eefc9887feb98679266ac1
* Add x86 power state machineRandall Spangler2012-01-171-1/+5
| | | | | | | | | | | For bringup, this powers on the x86 unconditionally. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
* GPIO interrupts are disabled by defaultRandall Spangler2012-01-131-0/+8
| | | | | | | | | | | | | Added gpio_enable_interrupt() to enable them. This ensures that a module which handles GPIO interrupts doesn't get them until it's ready. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7456 TEST=toggle power button while rebooting; without this fix it triggers a hard fault. Change-Id: I35d926053963a70dd9246ce46a4913603b2b2489
* Move board-specific GPIO lists to board-specific filesRandall Spangler2012-01-121-67/+34
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I47fd5d709a9575e41fdcdf21a7440ebbb762cef5
* Configure all GPIOsRandall Spangler2012-01-121-0/+2
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I0a9be4c689fb72507edcf202073b23c58902d7de
* Tidy GPIO configuration and board-specific configs for modules.Randall Spangler2012-01-121-3/+6
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: Ia06707db78ea9a9313b49a93e8732a7fc9fcc191
* Add constants for all GPIOs.Randall Spangler2012-01-111-8/+62
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I3b77cbbb7f0cc12a4daae7ababd603b5d7af32d1
* Add JTAG moduleRandall Spangler2012-01-111-0/+16
| | | | | | | | | | | This just ensures the JTAG pins are reset to JTAG function on warm reboot. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7448 TEST=none Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
* Add GPIO get/set commandsRandall Spangler2012-01-111-3/+5
| | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=from debug console, gpioget --> prints current level. Run a few times to see DEBUG_LED value toggle. gpioset debug_led 1 --> turns debug LED on. Run repeatedly to override the idle task toggling it off. Change-Id: I7c64044228697e052a9c20eb052d37a1f640f6e7
* Split power button code into its own fileRandall Spangler2012-01-102-6/+31
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7499 TEST=press and release power button; should see debug messages Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
* Clean up labels and TODOsRandall Spangler2012-01-101-2/+2
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: I8d6e99b3e2b60d32ea3719468590b055e692a67e
* Add EC host command to control fan speed.Vic Yang2011-12-272-0/+34
| | | | | | | | | | Add LPC host command to get and set fan speed. BUG=chrome-os-partner:7313 TEST=Connect a fan and manually test fan actual speed matches target speed. Change-Id: I4b6a711a1b8cca0dbd1c1936fe4f0f15240d3453
* Add host command to read temperature sensor valueVic Yang2011-12-222-0/+31
| | | | | | | | | | | | Add a LPC host command to read temperature sensor value with given sensor id. Add ectool command to read temperature sensor value through LPC. BUG=chrome-os-partner:7329 TEST=Manual check the reading received is the same as value printed by console command. Change-Id: Id3386774435be6c3ae010a143f4fa894568efdb8
* Use #defined constants for IRQ namesRandall Spangler2011-12-191-3/+4
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: If07ac671cef6b9d0e9fe0a96bf04455a3d2626ff
* Add IRQ constants, and task functions to enable/disable/trigger IRQs.Randall Spangler2011-12-121-6/+20
| | | | | | | | | | | | | The constants don't work with the DECLARE_IRQ() macro yet, because it relies on stringizing the IRQ number. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: Ie6ddecd79e28c319b095089131579ba994a17da3 (cherry picked from commit e24904644a977f2618f51629cc066b93a3d53595)
* Clean up UART codeRandall Spangler2011-12-122-0/+15
| | | | | | | | | | | | LPC module no longer directly talks to UART registers, and vice-versa. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='ectool sertest' on target system Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648 (cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
* Support flash checksum command for re-transmit.Louis Yung-Chieh Lo2011-12-122-0/+28
| | | | | | | | | | | The LPC is not stable enough to test. Kodus Rong. He creates this idea to checksum the partial content of flash for read/write/erase. This can improve the robustness of flashrom. BUG=none TEST=Tested with flashrom. Change-Id: I2a2f7b698a94674c03cbd8e3f15caf34f8986399
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