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* cr50: add TPM vendor-specific commands to support EC-EFS2Namyoon Woo2020-02-221-0/+4
| | | | | | | | | | | | | | | | | | | Based on the design in go/ec-efs2, this patch adds two TPM vendor-specific commands: - VENDOR_CC_GET_BOOT_MODE - VENDOR_CC_RESET_EC BUG=b:141578322 BRANCH=cr50 TEST=tested with EC-EFS supporting EC/AP firmware. With CR50 dev image, tested with gsctool on Octopus and Helios by sending each of new vendor commands. Checked flash_ec working on Scarlet in bitbang mode. Change-Id: Ia8f38a7b9cc45b172a1a1ef7e216034e520b79c7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956409 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* read EC Firmware hash from kernel secdata during board initNamyoon Woo2020-02-223-1/+22
| | | | | | | | | | | | | | Cr50 reads EC Firmware hash from kernel secdata. This data shall be used for EC-EFS (Early Firmware Selection) procedure. BUG=chromium:1020578, b:148489182 BRANCH=cr50 TEST=none Change-Id: Id8942b5b49dd5b0412d198a12ee0bf87fd59d47f Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956159 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* restructure EC-EFS moduleNamyoon Woo2020-02-201-9/+11
| | | | | | | | | | | | | | | - add ec_efs, which tracks the system boot mode. - add ec_comm.h header file for EC-EFS related functions. - revised vboot.h header file. BUG=b:141143112 BRANCH=cr50 TEST=none Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* make DIOB3 interruptible and wakable for EC-EFS2Namyoon Woo2020-02-081-0/+1
| | | | | | | | | | | | | | | | | | | | | If the board supports EC-CR50 communication, Cr50 enables both rising/falling-edge triggered interrupt on DIOB3 pin and makes it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4. If the board does not support EC-CR50 communication, Cr50 connects GPIO_AP_FLASH_SELECT to DIOB3. If EC puts high on DIOB3 to activate EC-CR50 communication, CR50 enables UART_EC RX and TX. BUG=chromium:1035706 BRANCH=cr50 TEST=none Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add gpio_set_wakepin() to configure wake pinsMary Ruthven2020-02-071-2/+18
| | | | | | | | | | | | | | | | | | | | | | | Cr50 needs a cleaner way to enable and disable wakepins. This change adds gpio_set_wakepin() to enable the wake pin or disable. The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting wake-pin configuration. This patch increases the flash usage by 16 bytes. BUG=b:35587259 BRANCH=cr50 TEST=verify pinmux has the same output before and after the change on octopus. Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org> Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044355
* change members of enum ec_efs_boot_modestabilize-12881.B-cr50_stabNamyoon Woo2020-01-311-4/+4
| | | | | | | | | | | | | | | | | | | Bit assignment in this enum has been changed. * BIT(1) : NO_BOOT flag -> RECOVERY flag * BIT(0) : RECOVERY flag -> NO_BOOT flag For this change, two members of enum ec_efs_boot_mode are swapped. - EC_EFS_BOOT_MODE_NO_BOOT = 0x01, // used to be 0x02 - EC_EFS_BOOT_MODE_RECOVERY = 0x02, // used to be 0x01 BUG=b:141578322 BRANCH=cr50 TEST=make buildall -j Change-Id: I88c4ef02cabd7fc3840467f7ff07444865969b31 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2029200 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* vboot: add macros, enums, and struct for EC-EFS2Namyoon Woo2020-01-181-0/+65
| | | | | | | | | | | | | This CL defines new macros, an enum and a data structure for EC-EFS2 implementation. BUG=b:141143112 BRANCH=cr50 TEST=make buildall -j Change-Id: I0b5d634f8e040638b4c4ffef5c8519959c509577 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956158
* extend INT_AP_L pulseNamyoon Woo2020-01-161-0/+7
| | | | | | | | | | | | | | | | | This patch extends INT_AP_L pulses to be at least 6.5 micro seconds. It is a tentative solution to to meet Intel TGL/JSL requirement on interrupt duration. BUG=b:130515803 BRANCH=cr50 TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec with logic analyzer on Hatch. Checked dmesg and coreboot log has no TPM errors. Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* usb_mux: cleanup the usb_mux_get() functionVijay Hiremath2019-11-261-4/+2
| | | | | | | | | | | | | | Simplified the usb_mux_get() function and made the MUX info prints same as in ectool. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Iefb16e1dbd323afbe248b06fe9c53abc63be9a67 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931284 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: use symbolic names instead of magic numbersPaul Fagerburg2019-11-261-2/+20
| | | | | | | | | | | | | | | | | | | PD_DP_PIN_CAPS used a lot of magic numbers, which made it difficult to work out what it's doing. Added a comment about using the "receptacle type" field to deterimine whether the UFP_D or DFP_D pin assignments should be used, and replaced magic numbers with #define'd constants. BUG=None BRANCH=None TEST=`make -j buildall && ./util/flash_ec --board=kohaku` (or whatever board you're testing with), then verify that a USB-C dock with HDMI or DisplayPort still works. Change-Id: I1b5cf6d6cf7d0e1698bd7c727226f10f804ed5e9 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935088 Reviewed-by: Jett Rink <jettrink@chromium.org>
* host_command: clear any leftover dataJett Rink2019-11-261-1/+6
| | | | | | | | | | | | | | | We want to ensure that the entire buffer we may be sending back to the host from the EC does not contain any data from previous host command responses. Clear the data in common code so all chips do not have to implement this functionality. BRANCH=none BUG=b:144878983,chromium:1026994 TEST=new unit test shows cleared data Change-Id: I93ad4d36923ba1bf171f740e94830640d3fde3b0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930931
* usbc: make BB virtual mux retimer compatible with non-virtualDenis Brockus2019-11-254-58/+13
| | | | | | | | | | | | | | | | Changed the driver interface for BB virtual mux retimer to stop using global functions and use the usb_retimers array instead. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I56befaca1720eb2f4e0599a983629b4df45dc76b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928121 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* Reland "smart_battery: add smbus error checking support"Ting Shen2019-11-253-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of daccb3adea9394116d7ab2c807e4a360cb5a93a1 Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: http://crrev.com/c/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> BUG=b:138415463 TEST=in addition to the TESTs above, verified this CL boots on hatch(npcx chips), and reef_it8320(it83xx chips). BRANCH=master Change-Id: I67975eee677cfd6e383742d48103662372cac061 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913940 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPMv2: PD: Separately track each SOP and SOP' and SOP''Sam Hurst2019-11-241-2/+5
| | | | | | | | | | | | | | | | | | Tracked PD header spec. version for each port partner type. BUG=chromium:1023025 BRANCH=none TEST=make -j buildall Manual Testing: Connected PD2.0 source charger and made sure we talked PD2.0 Connected PD3.0 source charger and made sure we talked PD3.0 Connected apple 2019 PD2.0 dock with charger and made sure we downgraded from PD3.0 to PD2.0 Change-Id: I3b49d9630acf6c19101ac71334445890c78c4077 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907430 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: ServoV4 is not recognized appropriatelySam Hurst2019-11-221-0/+7
| | | | | | | | | | | | | | | | | | Configure the port as a SNK with PD in DebugAccessory.SNK state BUG=chromium:1020752 BRANCH=none TEST=make -j buildall Manual Test: 1: Connect Servo v4 with NeckTek charger pluged in DUT power port The DUT negotiates to 20V, and starts charging. Change-Id: Id44d566024b5016965f996435d11befdc1c53e98 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906993 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* battery : Define CONFIG_BATTERY_DEAD_UNTIL_VALUEYongBeum Ha2019-11-221-0/+7
| | | | | | | | | | | | | | | | It takes 850ms~950ms to get valid RSOC after battery wake-up. Sometimes battery FG returns garbage data(1%) as RSOC and 0 value of desired current / voltage. Add CONFIG_BATTERY_DEAD_UNTIL_VALUE to continue charging. BUG=b:138413964 BRANCH=None TEST=build & flash, check battery charging with dead battery Change-Id: I0cbe30aa973499b0c27faf9b6da03a0344ad1065 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918985 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Trogdor: Initial board commitWai-Hong Tam2019-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial commit for Trogdor. Use Cheza as a baseline. Make the change according to the schematic, e.g. * Reflect the GPIO change * Reflect the TCPC/PPC part change * Update the USB topology, e.g. no device mode support * Remove the detachable related code * Add keyboard support * Support keyboard backlight * Update the battery characteristic * Add initial support of muxing DP path * Support a single USB-A port * Change sensors from lid to base * Minor code style improvement BRANCH=None BUG=b:143616352 TEST=BOARD=trogdor make Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* doc: document USB_PID strategyJett Rink2019-11-221-1/+8
| | | | | | | | | | | | | | | | We want to have a single USB VID/PID per platform. If we need further granularity within a platform, then we can use the HW version field within the AMA VDO. BRANCH=none BUG=none TEST=none Change-Id: Ia32f8c2b41efc04e570c8f6d92b3e1307948863a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1910451 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Enable TCPC low power when port is looking for a connectionSam Hurst2019-11-213-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port is in a state where it is looking for a connection, to save power, we should put the TCPC in its low power mode and enable auto toggling. Low power mode can happen when DRP auto toggling, acting as a SNK only, or acting as a SRC only. BUG=chromium:1022217 BRANCH=none TEST=make -j buildall manual tests: 1: (S0) Nothing plugged in, port is drp and low power mode 2: (S5/S3/S0ix) Port is SNK only, and low power with nothing plugged in 3: (S3/S0ix) If TypeC sink was previously plugged in, port remains powered 4: (S5/S3/S0ix) TypeC source is recognized 5: (S3->S0) TypeC sink plugged in, port is powered when S0 is reached Low power exit test: Using this command from the AP console: ectool i2cread 8 2 0x16 0x0d Transfer failed with status=0x1 # This means the TCPC was asleep. On the EC console: 2019-11-21 09:50:24 [315.235538 TCPC p1 init ready] 2019-11-21 09:50:24 [315.236048 TCPC p1 Exit Low Power Mode] 2019-11-21 09:50:24 [315.242837 TCPC p1 init ready] 2019-11-21 09:50:24 [315.243229 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.246471 C1: Unattached.SNK] 2019-11-21 09:50:24 [315.252504 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.362878 C1: LowPowerMode] 2019-11-21 09:50:24 [315.363314 TCPC p1 Enter Low Power Mode] Change-Id: I7e853d05e0ece1f6b3031f17a18fcbf0d9a15a51 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904974 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: add enter_low_power_mode for retimer muxDenis Brockus2019-11-211-0/+9
| | | | | | | | | | BUG=b:139428185 BRANCH=none TEST=verify mode is set correctly when switching devices Change-Id: I3e40e0321cb1026180b7edc0bfe99439c13acafb Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922062
* cr50: remove flash nonvolatile counter spaceVadim Bendebury2019-11-211-4/+0
| | | | | | | | | | | | | | Counter implementation has been moved to the AP, no need to keep space for it in the flash. BUG=b:65253310 BRANCH=cr50, cr50-mp TEST=generated image uses 2048 bytes less than before this patch. Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Add support for ACVP tests of HMAC SHA-256 DRBGVadim Sukhomlinov2019-11-211-0/+5
| | | | | | | | | | | | | | | | | | | HMAC DRBG is used for U2F key generation, and as such is subject for ACVP tests. Expose DRBG Init, Generate and Seed commands for automated testing with externally provided test vectors. BUG=b:138578319 BRANCH=cr50 TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: Add TRNG_TEST command to download entropy samples for NIST testsVadim Sukhomlinov2019-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | NIST 800-90B Entropy assesment tests requires 1M of 8-bit samples for statistical tests. While it's possible to use TPM2_GetRandom command to get entropy on cr50 (there is no software postprocessing), this command is not available when compiled with CRYPTO_TEST=1 due to lack of space in firmware. Adding vendor command which is available with CRYPTO_TEST=1 to get raw entropy from TRNG. Added support script to save entropy in file for further analysis. Since downloading entropy takes a long time, new option'-t' added to tpmtest.py which only invokes download of TRNG samples BUG=b:138577834 BRANCH=cr50 TEST=make BOARD=cr50 CRYPTO_TEST=1 && test/tpm_test/tpmtest.py -t To run NIST tests: nist_entropy.sh Change-Id: I237a4581332a6e2c0332fe6ecf40731ab0be3355 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919640 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* driver/ioexpander_it8801: add I/O expander driver for keyboardtim2019-11-191-0/+5
| | | | | | | | | | | | | | IT8801 is an I/O expander with a keyboard matrix controller. BUG=b:133200075 BRANCH=none TEST=Press any key on keyboard and the console command "ksstate on" can print keyboard scan state. Change-Id: I6903aad1eacfdfb6a7c6c04e6954a14e8c8caaac Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677976
* keyscan: decouple keyboard_raw functionality from the presence of TASK_KEYSCANAlexandru M Stan2019-11-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | With the addition of external i2c keyboard controllers, chips that don't necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN. Therefore it's wrong to assume we want the chip/*/keyboard_raw code included. There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW) that could get #undefd in strategic places. The place that would always define it would be in include/config.h but I don't believe that executes before the build.mk rules. BUG=b:135895590 TEST=Other boards with keyboards still happy. TEST=No compile errors (regarding missing keyboard GPIOS) when declaring TASK_KEYSCAN on a fresh stm32 board. BRANCH=master Change-Id: I061812a6941a11784950280648912edd5844bd79 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Create cometlake-discrete power driverPeter Marheine2019-11-181-0/+4
| | | | | | | | | | | | | | This sets up the driver (mostly copied from cometlake for now), to be used by puff. BUG=b:143188569 TEST=make buildall still succeeds BRANCH=none Change-Id: I4a4b70dd8ba58c070e2c6ad5941911bab16bafe6 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906391 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* chgstv2: stop charging when battery temp exceeds specsPaul Fagerburg2019-11-151-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Add a check for the battery temperature in the safe range to charge the battery, and if it isn't, stop charging. The battery information defines minimum and maximum temperatures for discharge and for charge. The state machine already checks if the battery temperature is outside of the range for discharge (as part of is_battery_critical) and will shut down the system completely if the battery temperature is out of range. However, the temperature range for charging is usually tigheter than for discharging, and it can be safe to discharge, but unsafe to charge. For example, Kohaku specifies a maximum charge temperature of 55 C, and a maximum discharge temperature of 60 C. If the battery is at 57 C, we don't want to charge, but it's still OK to use the system. The check is enabled by CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS. BUG=b:140596424 BRANCH=None TEST=`make buildall -j` builds with no errors. No boards have enabled CONFIG_BATTERY_CHECK_CHARGE_TEMP_LIMITS, so no effect. Change-Id: I3b76eab942ca3ef3871f0909395e91634db5640e Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1914510 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* icelake/tigerlake: add option to enable PP3300 before PP5000Keith Short2019-11-151-0/+7
| | | | | | | | | | | | | | | On Volteer, to avoid leakage from PP3300_A rail to PP5000 rail, turn on the PP3300 rail before PP5000. BUG=none BRANCH=none TEST=make buildall -j TEST=verify Volteer transitions to S0 Change-Id: Ic86f97dbdde6d6c904fe7efc8b0edc1ead727cf6 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918603 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* mock: Change mock initializer to compound literalCraig Hesling2019-11-153-3/+3
| | | | | | | | | | | | | | This ensures that these initializer/reset macros can be used as a reset value (after initialization). BRANCH=nocturne,nami BUG=none TEST=make buildall -j Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I5f4675399c87d959235b09e04c04e3613834421a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1917580 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Add driver for TI INA3221 voltage sensors.Andrew McRae2019-11-141-2/+4
| | | | | | | | | | | | | | | | | Add driver for TI INA3221 voltage sensors. Puff has several of these devices, and the EC has access to them. BRANCH=none BUG=b:144132145 TEST=EC buildall, tests Change-Id: I37efd6ce7f154339f002c633e5daf6a18fef05aa Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1903629 Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* usbc: retimer pi3dpx1207Denis Brockus2019-11-142-1/+62
| | | | | | | | | | | BUG=b:139428185 BRANCH=none TEST=verify mode is set correctly when switching devices Change-Id: Ic9d460a94bb8007f17168ac5237a4dcbc24cfb2b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900123 Reviewed-by: Edward Hill <ecgh@chromium.org>
* retimer: usbc retimer name cleanupDenis Brockus2019-11-132-8/+21
| | | | | | | | | | | | | | Need to cleanup naming around USBC Retimers for adding PI2DPX1207 code BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7e18e0abbe5bfd89bf0e20fa7b5174669689778f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911296 Reviewed-by: Edward Hill <ecgh@chromium.org>
* Clean up double tap related definitionHeng-Ruey Hsu2019-11-131-3/+3
| | | | | | | | | | | | | | | | Fixes: commit 2f2a81079191ca "Add double tap and make motion sense wake up ap" CONFIG_GESTURE_DETECTION_MASK includes significant motion in activity list. We cannot use it for double tap. Add more flags to distinguish it. BUG=b:135575671 BRANCH=kukui TEST=AP can receive mkbp event when double tap is triggered Change-Id: I13776a01b14dc251396a615c8c97353f2d0477d4 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911263 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: Refactor motion_sense_fifoYuval Peress2019-11-112-30/+60
| | | | | | | | | | | | | | | | | This change refactors the motion_sense_fifo to uniformly prefix all the functions to avoid collisions. It also adds several unit tests and fixes a few bugs with the fifo logic. BUG=b:137758297 BRANCH=kukui TEST=buildall TEST=run CTS on arcada, kohaku, and kukui TEST=boot kohaku (verify tablet mode works as expected) Change-Id: I6e8492ae5fa474d0aa870088ab56f76b220a73e3 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835221 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Add double tap and make motion sense wake up apHeng-Ruey Hsu2019-11-111-0/+4
| | | | | | | | | | | | | | | Change to use CONFIG_GESTURE_DETECTION_MASK since CONFIG_GESTURE_SENSOR_BATTERY_TAP and CONFIG_GESTURE_SENSOR_DOUBLE_TAP both define it. BUG=b:135575671 BRANCH=none TEST=build pass. EC can receive double tap interrupt. Change-Id: I6eec40ef7405ec0653ff62dbce98f975cb19e332 Signed-off-by: Heng-Ruey Hsu <henryhsu@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710210 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Add a board specific helper to return USB PD port countKarthikeyan Ramasubramanian2019-11-091-0/+17
| | | | | | | | | | | | | | | | | | | | | Certain SKUs of certain boards have less number of USB PD ports than configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable board specific helper to return the number of USB PD ports. This helps to avoid initiating a PD firmware update in SKUs where there are less number of USB PD ports. Also update charge manager to ensure that absent/ invalid PD ports are skipped during port initialization and management. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* ish: chip enablement of ish5.4 on tgl rvp platformLeifu Zhao2019-11-091-0/+16
| | | | | | | | | | | | | | | | | Chip level enablement of ish5.4 on tgl rvp platform. BUG=b:141519691 BRANCH=none TEST=tested on tgl rvp Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* gpio: Add UNUSED declaration for gpio.incCraig Hesling2019-11-083-0/+48
| | | | | | | | | | | | | | | | | | | | This new gpio.inc macro is intended to mark pins that are unused on a given board. This allows the chip implementation to configure them for the lowest power configuration. This CL brings immediate functional change. A reference implementation is provided for the STM32F4 chip family in crrev.com/c/1894242. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j Change-Id: I0bc0a63401ae8f3bba4108b5b9f9ced26785f2bc Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898796 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec_commands: Force enum to be at least 16 bitsTom Hughes2019-11-081-3/+5
| | | | | | | | | | | | | | | | | | If the values in the enum can fit in a byte, the compiler can optimize the size of the enum to a byte. However, our protocol requires 16 bits, so define a max enum value that forces at least 16 bits. BRANCH=none BUG=b:144056522 TEST=make buildall -j Change-Id: I119d990f2775d8b970ec0ec15df1e451fc5dc45d Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902679 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* Revert "usbc: remove unnecessary tcpc CC reads"Sam Hurst2019-11-061-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bec03d91bc9f954682c02d122a0500d10cc102c2. Reason for revert: Some TCPC's bugs will generate an attach event when nothing is connected, triggering the state machine to enter an attached state. Example output with nothing connected to the port: 2019-10-28 10:23:20 [0.044393 C1: Unattached.SNK] 2019-10-28 10:23:20 [0.101264 p1: PPC init'd.] 2019-10-28 10:23:20 [0.106488 C1: Unattached.SRC] 2019-10-28 10:23:20 [0.116072 C1: AttachWait.SRC] 2019-10-28 10:23:20 [0.220006 C1: Attached.SRC] TOT has basic TypeC/PD functionality but issues still exist that will be fixed in subsequent CLs. Original change's description: > usbc: remove unnecessary tcpc CC reads > > We only need to read the CC pins when the CC evt is fired otherwise the > CC pins should have the same value. It is actually incorrect/undesirable > that our old PD stack queried the tpcp cc driver over i2c so frequently > for the CC pins status. > > Also single source code that interprets the CC lines values into a UFP > or DFP state. > > Lastly, remove extraneous timers for cc debouncing, we only need one. > > BRANCH=none > BUG=none > TEST=builds > > Change-Id: I65baa2e6fb92d7ab5ca12daa76225cd13b9ab974 > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1825504 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Sam Hurst <shurst@google.com> > Commit-Queue: Denis Brockus <dbrockus@chromium.org> Bug: none Change-Id: Ie9bd366dd85df9a33934e06e4208543f6e7aaa9b Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900058 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ec-fans: Make fans configuration const by default.Andrew McRae2019-11-022-0/+9
| | | | | | | | | | | | | | | | It was pointed out to me that the fans config list was non-const, but there is only 2 boards that require non-const configuration, so by default make it const, but allow an override. BRANCH=none BUG=None TEST=EC compiles, make tests, buildall Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025 Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* Revert "usbc: update CRCReceiveTimer"Sam Hurst2019-11-021-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1092c786f7876745ec0d68dd52284d252e1abee5. Reason for revert: <Several Fluffy tests failed due to this CL> Original change's description: > usbc: update CRCReceiveTimer > > Shorten the CRCReceiveTimer and document that either the pe send or > error function will get called in response to a prl_ send message. > > BRANCH=none > BUG=none > TEST=build; > > Change-Id: Icc43886cadfdcd67c943b25aebfdfb55b2693ade > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1825514 > Tested-by: Denis Brockus <dbrockus@chromium.org> > Commit-Queue: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Reviewed-by: Edward Hill <ecgh@chromium.org> Bug: none Change-Id: I2051b6c2f3f36d5d0612f24ba08f9843f9487f66 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894765 Reviewed-by: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* servo_v4: The polarity is based on the flags in SRC DTS modeWai-Hong Tam2019-11-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port in SRC DTS mode, it should not perform the polarity detection. The polarity is predetermined, as a board-specific setting. In the servo case, the polarity is based on the flags. This CL changes the protocol layer to check the port in SRC DTS mode and call the board-specific function board_get_src_dts_polarity() for the polarity. BRANCH=servo BUG=b:140876537 TEST=Configed servo as srcdts and unflipped direction: > cc srcdts cc2 Verified the power negotiation good and detected the correct polarity: > pd 1 state Port C1 CC2, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e Without this patch, it detected the wrong polarity and the power negotiation failed: > pd 1 state Port C1 CC1, Ena - Role: SRC-DFP State: SRC_DISCOVERY, Flags: 0x10608 Change-Id: I32c5dfffeaeb20a21db1417f3a1c98566b7f5e38 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891255 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-015-10/+10
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* puff: Scrub config and generate hardware structuresAndrew McRae2019-11-011-1/+1
| | | | | | | | | | | | | | | | | | Verify all CONFIG items in board/puff/board.h. Generate the necessary hardware reference structures in board.c Generate the minimum GPIO references in order to build cleanly. v2: Remove some of the fan and temp sensors config. BUG=b:143564865 TEST=Compile and link EC image. Change-Id: Ibc073718ad1c85705ab460d96202799f8c4fea06 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893013 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* gpio: add function to set a GPIO and log to the consoleKeith Short2019-11-011-0/+11
| | | | | | | | | | | | | | Add a common function gpio_set_level_verbose() to generate a cprints() statement prior to changing the GPIO pin level. BUG=none BRANCH=none TEST=make buildall Change-Id: I6b3a9e89604fb721d8fa5208ce96df9e9414cdf9 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893633 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-3/+20
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* Cleanup: Renaming pd_is_ufp to pd_partner_is_ufpAyushee2019-11-011-2/+2
| | | | | | | | | | | | | | | | pd_is_ufp function returns port partner CC status, renaming it to pd_partner_is_ufp to avoid ambiguity between host and port partner's CC status. BUG=b:141971044 BRANCH=None TEST=make buildall -j Change-Id: I19da8c8470db134e438271b92918994d77e4eb5d Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894119 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* usbc: Get current DP pin mode and CC stateAyushee2019-11-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | To configure Intel virtual mux and burnside bridge retimer, current DP pin mode, cc state and the type of the cable is required. Hence, implemented a board level function that returns the current DP pin mode and added a function that returns the type of cable inaccordance to the cable vdo response. Also added a new version to USB_PD_CONTROL host command, to return the DP mode, cc_state and the cable type BUG=b:141971044 BRANCH=None TEST=Verifed with ectool usbpd command on CPU console, able to get correct CC state, pin mode and cable type Pin mode: USB:0x0 (No DP) DP cable:0x4 (Mode:C) USBC dock:0x8 (Mode:D) Change-Id: If87ae6b77e5fa2ceaa22319dfa2d2c802460edfa Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835030 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: add ceil_for function to math_util.hLeifu Zhao2019-10-311-0/+11
| | | | | | | | | | | | | | | | | | During code review for tgl rvp enablement, found it is better to add ceil_for function to math_util.h. BUG=none BRANCH=none TEST=successfully compile for arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Iee350881c88e923c7a70317a9b8d75ee6104dba0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873349 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
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