| Commit message (Collapse) | Author | Age | Files | Lines |
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This removes a TODO for b/179524867. We have determined that no special
handling needs to be performed in chipset_handle_espi_reset_assert.
BRANCH=none
BUG=b:179524867
TEST=buildall passes
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: I6d40b6119e3bef613e5ba2d9adfa986b79be9078
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2798982
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This provides support for the Intel Alder Lake SoC in conjunction with
the Silergy SLG4BD44540 power sequencer.
A new config option (CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) is provided
to enable this setup.
This is intended to be used by brya and its variants. Other Alder Lake
boards that use the Ice Lake style power sequencing are not affected by
this new config option.
BRANCH=none
BUG=b:173575131,b:177275055,b:177277633
TEST=buildall passes
Change-Id: I74c36f06fc8ad26c163093753140a5ca242d75c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675309
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This clones the icelake power sequencer code as a baseline for brya's
custom power sequencer. This is solely intended to highlight the
customizations in following patches.
BRANCH=none
BUG=b:173575131
TEST=buildall passes
Change-Id: Ib9f0b986ab617002f987fed26e8aba1f9322a3e1
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675308
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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