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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-524/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* AMD: Ignore forced shutdown if transitioningDiana Z2021-07-021-1/+1
| | | | | | | | | | | | | | | | | | | Ignore new forced shutdown requests if we're in the process of transitioning to off already. Otherwise, the power button press may turn the system back on again. BRANCH=None BUG=b:192463842 TEST=on guybrush, run the battery down to 2% in S0 and observe that we can successfully enter G3 even when additional chipset_force_shutdown() commands come through during the transition Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie2c83db939fe1cc8b3258903e209cba6394027fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000849 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* amd_x86: Check for S0ix before S3Rob Barnes2021-04-271-3/+6
| | | | | | | | | | | | | | | Cezanne is asserting both SLP_S0 and SLP_S3 for S0ix. On Intel only SLP_S3 is asserted. Move check for S0ix before check for S0 so EC enters correct power state. BUG=b:186135411 TEST=EC reports S0ix power state BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I47ede14e8031ba4d6a01399f2501801e597a6b1f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847332 Reviewed-by: Diana Z <dzigterman@chromium.org>
* AMD Power: Remove reference to S5 pauseDiana Z2021-04-121-3/+0
| | | | | | | | | | | | | | | | | The AMD power states don't actually reference the S5 pause variable, and instead always pause in S5 when power transitioning. It appears only braswell and samus power transitions actually use this pause to change their power sequencing. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0bdaa714fa41a696a8e446b04a62aba793e59432 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2818527 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* guybrush: Enable CONFIG_CHIPSET_X86_RSMRST_DELAYRob Barnes2021-03-161-0/+4
| | | | | | | | | | | | | | | | Add a delay of 10ms between S5_PGOOD and RSMRST_L. Needed to meet timing specs. 10ms matches what is used on Intel. This may need to be tuned for AMD chipsets. BUG=b:182802230 TEST=Build BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I8e2c5a2b47866496a1ae598089e4ac5aa5fa45d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2764971 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* guybrush: Enable S0ix for amd_x86Rob Barnes2021-02-121-0/+220
| | | | | | | | | | | | | | | | | Enable S0ix for amd_x86. This closely follows the intel_x86.c implementation. b/179294969 tracks merging intel_x86.c and amd_x86.c BUG=b:175234270 BRANCH=None TEST=Build for Guybrush Boot Zork, enter and leave suspend. Note, Zork does not support S0ix Change-Id: I874d2e9019fcc162c7ebfb6091b179ba482a4e47 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673905 Reviewed-by: Diana Z <dzigterman@chromium.org>
* power: Rename stoney.c to amd_x86.cRob Barnes2021-02-101-0/+300
Rename stoney.c to amd_x86.c since it covers all currently supported AMD chipsets. Add CHIPSET_CEZANNE to guard any differences between STONEY and CEZANNE chipsets. BUG=b:175234270 BRANCH=None TEST=Build for zork and guybrush Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I96f82127729d64970b8d46fc8ef4ddba6489dd8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2683923 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
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