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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-183/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-1/+47
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reset: Log the reason for AP resets.Jonathan Brandmeyer2018-07-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a new EC host command 'uptime info' which gathers up some information which may be useful for debugging spurious resets on the AP (was the EC reset recently? Why was the EC reset? If the EC reset the AP, why did it do so?, etc.). Provide ectool support for the same. Example results of `ectool uptimeinfo`: ``` localhost ~ # ectool uptimeinfo EC uptime: 475.368 seconds AP resets since EC boot: 2 Most recent AP reset causes: 315.903: reset: console command 363.507: reset: keyboard warm reboot EC reset flags at last EC boot: reset-pin | sysjump ``` BRANCH=none TEST=Perform some `apreset` commands from the EC console and observe their side-effects via the `ectool uptimeinfo` command on the AP side. Test sequences include no-resets through 5 resets, observing that the ring buffer handling was correct. BUG=b:110788201, b:79529789 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I0bf29d69de471c64f905ee8aa070b15b4f34f2ba Reviewed-on: https://chromium-review.googlesource.com/1139028 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Clean up UART buffer before shutdownVijay Hiremath2018-05-231-0/+8
| | | | | | | | | | | | | | | | | | | | UART buffer gets overwritten by other tasks if it is not explicitly flushed before printing it on the console by same task. Hence, clean up the UART buffer so that all the debug messages are printed on the UART console before doing shutdown. BUG=b:79950369 BRANCH=none TEST=Manually tested on BIP, observed that UART logs are not lost on the terminal when apshutdown is issued. Change-Id: I420e9de9e2e71913ee3168267a6f3a2728b2690b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1064977 Commit-Ready: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-191-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-251-12/+0
| | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* apollolake: Remove AP cold reset logicVijay Hiremath2018-03-251-29/+8
| | | | | | | | | | | | | | | | | | | | | In APL & GLK, cold reset code does a AP force shutdown (with board specific AP shutdown code) by power sequencing the SOC all the way to S5 and bring it back to S0. However there is no separate GPIO in APL & GLK for doing AP cold reset hence removed the AP cold reset logic. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually verified on GLKRVP, apreset cold & warm behave same Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974107 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-2/+2
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMIShamile Khan2018-01-161-0/+4
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=GLKRVP can boot to OS when a coreboot image with eSPI enabled is flashed. Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/818196 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* intel_x86: Handle RSMRST signal in Intel x86 common codeVijay Hiremath2017-01-211-23/+1
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427018 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Group Intel x86 power sequencing common codeVijay Hiremath2017-01-201-269/+23
| | | | | | | | | | | | | | | | | | | Grouping the Intel x86 power sequencing common code so that the future chipset power sequencing implementation can make use of the existing code. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Manually tested on Reef & Chell. System can boot to OS. S3, S5, hibernate are working. Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/402272 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Extract Intel x86 power sequencing common codeVijay Hiremath2017-01-071-87/+11
| | | | | | | | | | | | | | | | | Extracted Intel x86 power sequencing common code from skylake.c and apollolake.c to implement common code for power sequencing. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/406486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* apollolake: Add support to enable eSPI signalsVijay Hiremath2017-01-061-6/+32
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I6d90d647a6e19c627aa68ddd8a203d6be8b2e32d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425820 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Apollolake: Enter/exit from S0ix based on host commands from kernelArchana Patni2016-11-171-61/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the entry/exit model for S0ix from a PCH SLP_S0 signal based model to a hybrid host event/direct interrupt model. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. The assertion of SLP_S0 comes later than HC(suspend) and deasserion of SLP_S0 comes earlier than HC(resume). ________ ________ SLP_S0 |______________________| _____ ________ HC |___________________________| BRANCH=none BUG=chrome-os-partner:58740 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify idle state transitions during display off and periodic wakes from S0ix do not lead to state transitions in EC. Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/401072 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* apollolake: Do not power-on AP till sufficient power is providedVijay Hiremath2016-08-241-3/+3
| | | | | | | | | | | | | | | | | Do not power-on the AP unless battery can provide sufficient power or the charger is negotiated to sufficient power. BUG=chrome-os-partner:56494 BRANCH=none TEST=Manually tested on Reef. Device can boot to OS without the battery & cut-off battery. Change-Id: Ib22bad81a29ccbb2fecc8e835148b627dd722988 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/374023 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* apollolake: modify PMIC_EN and RSMRST_N handlingKevin K Wong2016-05-271-19/+38
| | | | | | | | | | | | | | | | | | | | | | Move power rail and pmic enable control to be handled at board level due to specific board design. Modify rsmrst where assertion is pass-through at all time and de-assertion is only pass-through at power up. BUG=chrome-os-partner:53666 BRANCH=none TEST=amenia is able to handle apreset warm/cold, pmic shutdown, soc reset/shutdown. Change-Id: I7ff819d88d0e194073bee8f02b1e3fa70ca44ba7 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/347370 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* reef: Initial commitDavid Hendricks2016-05-201-4/+10
| | | | | | | | | | | | | | | | This adds the basic framework for Reef including full GPIO listing, board config file, and rudimentary functionality. It has not been fully tested and still has several TODOs/FIXMEs. For now we just need something that will build and can be incrementally improved. BUG=chrome-os-partner:53035 BRANCH=none TEST=EC and AP both boot, seems reasonably stable for now Change-Id: I4934ad00917e251dd1d7eb759207a92c45a36136 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339292 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* apollolake: ignore PLTRST# from SOC unless RSMRST# is deassertedKevin K Wong2016-05-031-0/+15
| | | | | | | | | | | | | add optional chipset specific function to check if PLTRST# is valid BUG=chrome-os-partner:52656 BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341732 Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: Remove timing delay for SOC_PWROK and RSMRST_NKevin K Wong2016-04-151-10/+3
| | | | | | | | | | | | | | | | | | | | | PMIC already has a built-in 100ms delay for V1P05S when ALL_SYS_PWRGD asserts, hence EC can assert SOC_PWROK immediately. On shutdown RSMRST_N should assert and SOC_PWR_OK should de-assert immediately when PMIC asserts PMIC_RSMRST_N and de-assert All_SYS_PWRGD respectively. Hence removed the unnecessary timing delay for SOC_PWROK and RSMRST_N. BUG=none BRANCH=none TEST=Issued a shutdown command and manually tested on amenia. RSMRST_N asserts immediately when PMIC asserts PMIC_RSMRST_N SOC_PWR_OK de-asserts immediately when PMIC de-asserts All_SYS_PWRGD. Change-Id: I8bb79277a3dcf8545764ba58736f422ac377776e Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/339001 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: initial chipset codeKevin K Wong2016-03-311-0/+459
used chipset skylake as the initial code base for apollolake BUG=none BRANCH=none TEST=make buildall Change-Id: If82f9bcd53ff44714f4b277637ff9f3c115ccc4d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331651 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
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