| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are
called from the chipset task, while the system has already shut down
and all the suspend rails are already off.
It will be used for executing pending EC reboot at the chipset shutdown.
The EC reboot should be executed when the chipset is completely off.
BRANCH=None
BUG=b:156981868
TEST=Built all boards.
Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Provides a new EC host command 'uptime info' which gathers up some
information which may be useful for debugging spurious resets on the AP
(was the EC reset recently? Why was the EC reset? If the EC reset the
AP, why did it do so?, etc.). Provide ectool support for the same.
Example results of `ectool uptimeinfo`:
```
localhost ~ # ectool uptimeinfo
EC uptime: 475.368 seconds
AP resets since EC boot: 2
Most recent AP reset causes:
315.903: reset: console command
363.507: reset: keyboard warm reboot
EC reset flags at last EC boot: reset-pin | sysjump
```
BRANCH=none
TEST=Perform some `apreset` commands from the EC console and observe
their side-effects via the `ectool uptimeinfo` command on the AP side.
Test sequences include no-resets through 5 resets, observing that the
ring buffer handling was correct.
BUG=b:110788201, b:79529789
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Change-Id: I0bf29d69de471c64f905ee8aa070b15b4f34f2ba
Reviewed-on: https://chromium-review.googlesource.com/1139028
Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The common x86 chipset code assumed that CPU_PROCHOT was active high,
however on some boards it's actually active low. This commit simply
adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts
the places where the signal is used.
BUG=b:109882953
BRANCH=poppy
TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted
by default.
Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1092150
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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this is to move the existing code from chipset level to board level
since PseudoG3 is a board feature that required specific hardware.
BUG=none
BRANCH=glados
TEST=use hibernate command to enter PseudoG3
Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/327677
Reviewed-by: Shawn N <shawnn@chromium.org>
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In case of 'apshutdown', during transition to S5 state,
GPIO_PCH_SLP_S4_L signal was not getting deasserted but
required rail went away (GPIO_PCH_SYS_PWROK). So it was
going on a loop S5 -> S3 and S3 -> S5.
In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence
conditinally setting it based on CONFIG_PMIC
BUG=none
TEST=apshutdown on strago
BRANCH=none
Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c
Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292024
Reviewed-by: Shawn N <shawnn@chromium.org>
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In case of 'apshutdown', SOC loses power immediately
while EC is waiting for SOC's PMC_SUSPWRDNACK signal
forever.
BUG=chrome-os-partner:43038
TEST=Cyan
BRANCH=none
Change-Id: I34321d00a89011e90222ea5916a42e9a51d4f4b0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288203
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
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Added support for PMIC in Braswell power sequencing code to support
the PMIC enabled Braswell devices.
BUG=none
TEST=Tested S3, S5, G3 & PG3 on BCRD2.
BRANCH=none
Change-Id: I247ef9506d0e8065c761bfb00b9141ec8ff5ada8
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283579
Reviewed-by: Shawn N <shawnn@chromium.org>
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Removed USB enable/disable as it will be handled by
HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled.
BUG=none
TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value
changed when state switch between S3 and S5.
BRANCH=none
Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283593
Reviewed-by: Shawn N <shawnn@chromium.org>
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BUG=none
TEST=Tested on DVT 1.1, verified V3p3A is off in Pseudo G3
BRANCH=none
Change-Id: Id73b42d9f2e49239e82fad7931bbcc63e36a2c0b
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283602
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The USB power is off in S5 with previous ChromeBook.
The braswell platfrom should be the same as before.
BUG=chrome-os-partner:39507
BRANCH=cyan
TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console.
Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/267451
Reviewed-by: Shawn N <shawnn@chromium.org>
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The current power sequencing would shutdown the system
when suspend command or reboot was initiated from the kernal.
Proper transitions from S0-S3 and S3-S0 are handled.
BUG=None
BRANCH=None
TEST=Tested on Braswell reference design. Issued
commands from kernel:For shutdown - "shutdown -P now" and
suspend - "powerd_dbus_suspend"
Change-Id: I7cc734f29c0dca89f7d9564f175895467b405df0
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265091
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Eric Caruso <ejcaruso@chromium.org>
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Modules that are enabled are listed below:
- Power Sequencing
- Keyboard Scan and Protocol
- LPC to support Keyboard
- Power Button Task
ec.spi.bin has to be generated manualy using
pack_ec.py
BUG=None
BRANCH=None
TEST=Tested on Stargo-Proto board
Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226303
Reviewed-by: Vic Yang <victoryang@chromium.org>
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