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* Kindred: Fix reset trigger even system force to G3.David Huang2020-02-071-0/+11
| | | | | | | | | | | | | | | | | | System will trigger reset when already force to G3. Add board_chipset_forced_shutdown() in chipset_force_shutdown to stop reset when system force to G3. BUG=b:143440730 BRANCH=master TEST=Power on system and make system enter G3 immediately. Make sure system won't reset. Change-Id: Ie601921af9adf08d2055cdecb0243e64bd57724f Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014001 Tested-by: David Huang <david.huang@quanta.corp-partner.google.com> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Kindred: Add workaround for TI TPS51486RJER when system resumeDavid Huang2020-01-101-0/+11
| | | | | | | | | | | | | | | | Monitor GPIO PG_EC_ALL_SYS_PWRG was not trigger, when power on within 3 seond, EC will reset system. BUG=b:143440730 BRANCH=master TEST=check boot to OS was workable Change-Id: I19f2411a5369c75b6895316b791d077e2aee7deb Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948690 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com>
* cometlake: cleanup power signal namesKeith Short2019-10-311-20/+21
| | | | | | | | | | | | | | | Add X86 prefix to the Comet Lake signals names for consistency with other Intel APs. BUG=none BRANCH=none TEST=make buildall Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* cometlake: Cleanup GPIO_PCH_SYS_PWROKKeith Short2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | Change GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK on cometlake to conform with naming convention used on other Intel processors. Leave gpio.inc files unchanged and add a mapping from GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK in the board files. BUG=none BRANCH=none TEST=make buildall -j TEST=boot kohaku Change-Id: I722cb06dd90ee5d7e426664508f54a5cbe19de4a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848251 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* cometlake/icelake: cleanup GPIO_PCH_RSMRST_LKeith Short2019-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | Replaced references of GPIO_EC_PCH_RSMRST_L with GPIO_PCH_RSMRST_L in to match convention used in common Intel power sequencing. Boards still use GPIO_EC_PCH_RSMRST_L in their gpio.inc files to match schematic net names. BUG=none BRANCH=none TEST=buildall -j TEST=boot kohaku (cometlake device) TEST=run "apshutdown" on kohaku Change-Id: Ic9fa13dbf2d4e6c8953b82a9dd20f48a6cf8d2c8 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846690 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* cometlake: Remove TODO comment from chipset_force_shutdownScott Collyer2019-09-121-4/+0
| | | | | | | | | | | | | | | | | | There was a todo to replace a while loop with a call to power_wait_signals_timeout. However, using that function is not feasible in this case as it's only intended to check for power signals that are high. Removing the TODO comment since it's not applicable. BUG=b:122264541 BRANCH=None TEST=make BOARD=hatch Change-Id: I0dca060f8a8e00bc99a433d78dd55d262a867cb1 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1783521 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-1/+35
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cml: Remove while loop to check for PP5000_A_PG signalScott Collyer2019-05-241-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cometlake is sequencing from G3->S5, the 5000_A rail is enabled. After enabling the 5000_A rail there was a while() loop to wait for the 5000_A rail to go high. If for some reason this rail did not go high, then it would just loop there until a watchdog reset. This CL removes this while loop check and instead modifies the macro CHIPSET_G3S5_POWERUP_SIGNAL to include the PP5000_A_PG signal. The common intel_x86 power sequencing code already has a check just after the call to chipset_pre_init_callback. BUG=none BRANCH=none TEST=Manual If no battery is present and the bq25710 reset register bit is set, then PPVAR_VSYS gets set to ~4V which is not high enough to generate PP5000_A rail. In this state the EC would consistently watchdog loop when just as AP power sequencing was initiated by the EC. Verified with this CL, that while the PP5000_A rail still doesn't come up, that the EC no longer hits a watchdog and power signal failure is logged in the EC console. Change-Id: I02aab7ed4f4723ec0d3ae04e4b8093494877615f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1599674 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cometlake: Add PP5000_CONTROL config for PP5000_A railScott Collyer2019-03-161-6/+9
| | | | | | | | | | | | | | | | | | | This CL adds the config option CONFIG_POWER_PP5000_CONTROL to the instances where PP5000_A is turned on or off as part of power sequencing. This option is used for cases where the PP5000_A rail may need to stay on for bc1.2 detection even with the AP is in G3. BUG=b:122265772 BRANCH=none TEST=Verified that AP power sequencing still behaves as expected. Change-Id: Ia1acd5a592f60973a3b852a987e93283f10d0ac0 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1503956 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cometlake: pass RSMRST_L to PCH early to meet tPCH12Rachel Nancollas2019-03-141-0/+3
| | | | | | | | | | | | | | | | | | | tPCH12 dictates that _A rails should go low >= 400ns of RSMRST_L going low. Waiting for this to propagate through the power good chip and EC takes too long. This patch asserts RSMRST_L to the PCH as soon as we the chipset shuts down to meet this timing. BRANCH=none BUG=b:124924912 TEST=Veify on scope that PP3300_A goes low >= 400ns of EC_PCH_RSMRST_L going low during a regular shutdown. Change-Id: I7e6691159f58bc70a0078af53652f8efca3094ff Signed-off-by: Rachel Nancollas <rachelsn@google.com> Reviewed-on: https://chromium-review.googlesource.com/1520768 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cometlake: Guard passing RSMRST_L to PCH by PP5000_A railScott Collyer2019-02-041-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | RSMRST_L gets passed along to the AP by EC when it changes state. For low to high transitions the EC needs to ensure that the PP5000_A rail is up prior to passing the RSMRST_L transition to the AP. This CL adds a check to prevent calling common_intel_x86_handle_rsmrst() when RSMRST_L is high if the PP5000_A rail is not up. Since PP5000_PG signal will float high when the regulator is not powered at all, both the enable and power good signals are used to verify that PP5000_A rail is powered. BRANCH=none BUG=b:122631914 TEST=Verified on scope that RSMRST_L to PCH rising edge happens after PP5000_A rail rising. Change-Id: Icfd4dabbdfaf6ae76b3cdcbc6f75a5188a21ff51 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1406497 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cometlake: Add power sequencing support for cometlake chipsetScott Collyer2019-01-241-0/+137
This CL adds cometlake specific portions of power sequencing. BRANCH=none BUG=b:122251649 TEST=make buildall, verified in factory that AP gets to S0 Change-Id: I84726cd522ab55ca9ec095b94392ffa387fb253f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377570 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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