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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-325/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* icelake : fix power sequence behaviorJacky Wang2021-02-081-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove powerok signal checking the current GPIO level step. We found the GPIO_EC_AP_PCH_PWROK_OD did not setting to low when system shutdown. The signal EC_AP_PCH_PWROK_OD is connect with signal IMVP9_VRDAY_OD. The gpio_get_level get GPIO status from the EC register GPDMR and gpio_set_level set GPIO level by EC register GPDR. If signal IMVP9_VRDAY_OD is low, the EC GPDRM will read EC_AP_PCH_PWROK_OD status is low even the GPDR is set to High. We remove the signal status check to make sure power sequence is expected. BUG=b:171450533 BRANCH=firmware-dedede-13606.B TEST=BOARD=galtic Check system can power on. Signed-off-by: Jacky Wang <jacky5_wang@pegatron.corp-partner.google.com> Change-Id: Ia8d8c096b15c09644432736df5ca5fc10d91c954 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675322 Reviewed-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* JSL: Wait 60ms to turn off PP5000_U after PP3300_AAseda Aboagye2020-06-091-0/+7
| | | | | | | | | | | | | | | | | | | For Jasperlake, we need to wait 60ms after PP3300_A goes down before turning off PP5000_U. This time is needed to allow VCCIN AUX to discharge properly. BUG=b:157784504 BRANCH=None TEST=Build and flash waddledoo, verify that a 60ms delay is added when PP3300_A turns off when shutting down. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I0fc08bfd597c0e0264f4ff52ccec3a1504f9fb8e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229605 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* power/icelake: Don't cache GPIO_PCH_DSW_PWROKSooraj Govindan2020-05-181-3/+1
| | | | | | | | | | | | | | | | | | | | There is a potential race condition for passthrough DSW_PWROK pin as the PCH_DSW_PWROK is set to low by chipset_force_shutdown() and is not updated by dsw_pwrok_pass_thru(). To avoid this, use current values of EC_DSW_PWROK and PCH_DSW_PWROK to set the passthrough value. BUG=b:150985246 BRANCH=None TEST=`make -j buildall` Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Change-Id: I0249a948ea8814cbc3462630e99a471010a056df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204337 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLakeKeith Short2020-04-091-59/+60
| | | | | | | | | | | | | | | | | | | | | Configure PWROK generation related signals for Ice Lake, Tiger Lake, and Jasper Lake SoCs. The array driven sequencing provides better flexibility for the PWROK signals, some of which may be automatically handled by the platform and some require EC control. BUG=b:150726713 BRANCH=none TEST=make buildall TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and verify signals are deasserted when exiting S0. TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK, verified JPL sequences to S0. Change-Id: Iceae29c65398643839b31f6cd757352282849fda Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* icelake: Call hooks around RSMRST when shutting downAseda Aboagye2020-03-261-0/+3
| | | | | | | | | | | | | | | | | | | When we decide to force the chipset to shutdown, we were just simply asserting RSMRST_L which was bypassing the hooks around RSMRST (i.e. - board_has_before_rsmrst() and board_has_after_rsmsrt()). BUG=b:151680590 BRANCH=None TEST=Build and flash waddledoo, boot AP and shutdown, verify that PG_PP1050_ST is no longer asserted. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I8bc33ff12bf776dab7158bc2efac0637cebdaca4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2119590 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* power/icelake: Transition to G3 when S5 failsAseda Aboagye2020-03-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | This commit fixes a bug where we were forcefully setting the chipset state to G3 instead of transitioning to G3 from our failed S5 attempt. This was causing an issue where we had turned on some power rails in trying to reach S5, but when reaching S5 failed, we "assumed" G3 and therefore skipped turning off the rails we had enabled. BUG=b:151479266 BRANCH=hatch TEST=Build and flash on waddledoo that isn't booting to S0. Verify that PP3300_A and PP5000_U are turned off when the sequencing fails and that DPWROK is not asserted after the failure. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ic7af003270c239088b4364e82783aae56a45fa33 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2106372 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* volteer: Prevent glitch on SLP_S3_L during power onKeith Short2020-02-291-15/+36
| | | | | | | | | | | | | | | | | Reconfigure the SLP_S3_L power interrupt as an output and drive this signal low while the PP3300_A rail comes up. This prevents a glitch on the SLP_S3_L signal that can affect the power sequencing. BUG=b:143346794 BRANCH=none TEST=make buildall TEST=Verify Volteer boots. With debug code enabled, verify SLP_S3_L drives low while PP3300 turns on. Change-Id: Ic8204874cb9e68a1af27fafcf5274d50ce5cb38f Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068535 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* power/icelake: JSL: add wait loop for receiving ALL_SYS_PWRGDSooraj Govindan2020-02-191-0/+11
| | | | | | | | | | | | | | | | | | | | In some boot cycles, identified a case where PG_DRAM_OD not getting SET when EC already transitioned to S0. PG_DRAM_OD taking around 5+ms to get SET, after SLP_S3_L SET. In such cases, intel_x86_get_pg_ec_all_sys_pwrgd() returns 0 and PCH_SYS_PWROK remaining as 0. BUG=b:147257114 BRANCH=None TEST=make -j BOARD=waddledoo; flash waddledoo, verify that DUT can boot to S0. Change-Id: I09207c723d3d006e8a555c3c2d44aa6ed5cc027d Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054363 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* waddledoo:Handle EC_AP_PCH_PWROK_OD and ALL_SYS_PWRGDSooraj Govindan2020-02-191-5/+16
| | | | | | | | | | | | | | | | | | | | | | As per Waddledoo power sequencing requirements, 1. ALL_SYS_PWRGD should be driven based on DRAM power good and the PP1050_ST power good. 2. the EC needs to assert EC_AP_PCH_PWROK_OD, with a 2ms minimum delay after receiving the DRAM power good and the PP1050_ST power good. 3. Enable CONFIG_BACKLIGHT_LID BUG=b:147257114 BRANCH=None TEST=make -j BOARD=waddledoo; flash waddledoo, verify that DUT can boot to S0. Change-Id: I5ad226faa15cfe8ae569524decf405bbd378a28c Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044250 Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power/icelake: JSL: Handle EC_AP_VCCST_PWRGDAseda Aboagye2020-02-051-1/+23
| | | | | | | | | | | | | | | | | For Jasperlake, the EC needs to assert EC_AP_VCCST power good with a 2ms minimum delay after receiving the DRAM power good and the PP1050_ST power good. BUG=b:148688874 BRANCH=None TEST=`make -j buildall` Change-Id: Ieedabf5a8a7af3951910118504dc702f7f8058bc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036453 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* power/icelake: JSL: Drive VCCIO_EXT from SLP_S3_LAseda Aboagye2020-02-051-0/+10
| | | | | | | | | | | | | | | | | Per the power sequencing requirements, VCCIO_EXT, new for JSL, should be driven based off of SLP_S3_L deassertion/assertion. BUG=b:148630993 BRANCH=None TEST=Build and flash waddledoo, boot to S0, verify that VCCIO_EXT is enabled. Shutdown, verify it's disabled. Change-Id: I2a25b29ebbde94eabf6b71c5c02252ebbd6ad1d9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032728 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* icelake: Allow power good methods to be overiddenAseda Aboagye2020-01-081-4/+14
| | | | | | | | | | | | | | | | | | | | Jasperlake uses the same chipset driver as Icelake and the dedede reference design does not have a distinct pins for a couple of the power good signals. In order to accommodate this, this CL allows some of the power good signals to be overidden by a board specific implementation. These power good signals are PG_EC_DSW_PWROK and PG_ALL_SYS_PWRGD. BUG=b:147257114 BRANCH=None TEST=`make -j buildall` Change-Id: I3d889ed9d17bf224a69d1de188fe15933140d606 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1987836 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* icelake/tigerlake: add option to enable PP3300 before PP5000Keith Short2019-11-151-11/+20
| | | | | | | | | | | | | | | On Volteer, to avoid leakage from PP3300_A rail to PP5000 rail, turn on the PP3300 rail before PP5000. BUG=none BRANCH=none TEST=make buildall -j TEST=verify Volteer transitions to S0 Change-Id: Ic86f97dbdde6d6c904fe7efc8b0edc1ead727cf6 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918603 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* icelake/tigerlake: Add debug for setting main railsKeith Short2019-11-151-8/+16
| | | | | | | | | | | | | | | Add additional debug output for Ice Lake and Tiger Lake power sequencing when the CONFIG_BRINGUP option is enabled. BUG=none BRANCH=none TEST=make buildall TEST=Verify debug messages on Volteer when CONFIG_BRINGUP is enabled. Change-Id: I80fc23f470818af7a4dad73a7ad77bc9ba42d537 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918602 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-011-18/+52
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* icelake: Cleanup GPIO_PCH_DSW_PWROKKeith Short2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | Change GPIO_EC_PCH_DSW_PWROK to GPIO_PCH_DSW_PWROK to match convention for EC to PCH signals used by other Intel processors (specifically cannonlake already used GPIO_PCH_DSW_PWROK). BUG=none BRANCH=none TEST=buildall -j Change-Id: I59fb8d3ee3867c70dde74c186ba3974490c3cd27 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848252 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* cometlake/icelake: cleanup GPIO_PCH_RSMRST_LKeith Short2019-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | Replaced references of GPIO_EC_PCH_RSMRST_L with GPIO_PCH_RSMRST_L in to match convention used in common Intel power sequencing. Boards still use GPIO_EC_PCH_RSMRST_L in their gpio.inc files to match schematic net names. BUG=none BRANCH=none TEST=buildall -j TEST=boot kohaku (cometlake device) TEST=run "apshutdown" on kohaku Change-Id: Ic9fa13dbf2d4e6c8953b82a9dd20f48a6cf8d2c8 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846690 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-1/+35
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* icelake: Add option to turn-off 5V-rail in power sequencingVijay Hiremath2019-06-111-0/+14
| | | | | | | | | | | | | | | | | | | Need to enable or disable the 5V-rail in power sequencing to support boards with 5V-rail. This CL is a derivative of Cometlake CL. Change-Id: Ia1acd5a592f60973a3b852a987e93283f10d0ac0 Reviewed-on: https://chromium-review.googlesource.com/1503956 BUG=b:134688223 BRANCH=none TEST=Able to control 5V-rail of ICLRVP Change-Id: Iefaa1091e863c1c431ea784d2e02478ce67f8911 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647369 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ICL: Modify force_shutdown to meet PCH timing requirementsScott Collyer2018-09-051-3/+10
| | | | | | | | | | | | | | | | | | Time between RSMRST going low and the _A rails dropping 5% must be > 400 ns. To meet this timing set the PCH pass through low at beginning of chipset_force_shutdown. Similarly, set EC_PCH_DSW_PWROK low to meet its timing requirement relative to _A rails dropping 5%. BUG=b:112170058 BRANCH=none TEST=Verified that timing meets the specifications. Change-Id: I88573a4b926f5804d1a0df5702078eb32a6d0221 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179142 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ICL: Fix the timeout value for SUS_SLP_L in G3S5 stateScott Collyer2018-08-221-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | The function power_wait_signals_timeout() expects the timeout value to be in usec, but a value in msec was being passed in. In addition, measuring on a system shows that the signal wait is ~150 msec, so increased the timeout value to 250 mSec. BUG=b:112913718 BRANCH=none TEST=Verfied that with this change I no longer see the console message: SLP_SUS_L didn't go high! Assuming G3. powerinfo shows: > powerinfo [2470.263452 power state 3 = S0, in 0x003f] Change-Id: I6564cbab638b80234a2574f3f700d1f33c516de1 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1184330 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* icelake: Correct POWER_G3S5 exit statusVijay Hiremath2018-08-091-11/+4
| | | | | | | | | | | | | | | | | | For Icelake SLP_SUS_L deassertion is the exit state to go to POWER_S5 state hence corrected the logic to wait on SLP_SUS_L deassertion. BUG=b:111851944, b:111810925 BRANCH=none TEST=ICLRVP & Dragonegg can boot to S0 Change-Id: I65a04a448bb97223589f6d1338249c87ab395f42 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1162661 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* icelake: Add power sequencing support for icelakeScott Collyer2018-07-271-0/+145
This CL adds code to support x86 power sequencing for icelake. BRANCH=none CQ-DEPEND=I0bf29d69de471c64f905ee8aa070b15b4f34f2ba BUG=b:111121615,b:111853963 TEST=make buildall. Also tested on P0 and verified that AP gets to S0. Change-Id: I3513f2e598162b2362d56c33df76d16b63864bd3 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123318 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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