| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel_x86/power: Consolidate chipset specific power signals array | Vijay Hiremath | 2019-06-13 | 1 | -0/+13 |
| | | | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> | ||||
| * | icelake: Add power sequencing support for icelake | Scott Collyer | 2018-07-27 | 1 | -0/+29 |
| This CL adds code to support x86 power sequencing for icelake. BRANCH=none CQ-DEPEND=I0bf29d69de471c64f905ee8aa070b15b4f34f2ba BUG=b:111121615,b:111853963 TEST=make buildall. Also tested on P0 and verified that AP gets to S0. Change-Id: I3513f2e598162b2362d56c33df76d16b63864bd3 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123318 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> | |||||
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index : delta/coreboot/chrome-ec.git | |
| review.coreboot.org: chrome-ec.git |
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