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* volteer: Add RTC resetKeith Short2019-09-291-1/+9
| | | | | | | | | | | | | | | Add support for the RTC reset on Volteer. This change also deduplicates the board_rtc_reset() function which was identical on boards that enabled CONFIG_BOARD_HAS_RTC_RESET. BUG=b:141321096 BRANCH=none TEST=make buildall Change-Id: Ifc6959f8271400174fd4999a3c70800b03b9c2d0 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816869 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cometlake: Minimize delay for high->low rsmrst passthroughScott Collyer2019-09-041-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hatch designs buffer the PG_EC_RSMRST# signal from the Silego power good logic through the EC and out EC_PCH_RSMRST# to the SoC RSMRST# pin. For power off transitions, this should be as fast as possible, in the ns region if possible. However this time is ~1 msec. To reduce this delay as much as possible this CL introduces a new interrupt handler than can be linked to the rsmrst gpio signal. This interrupt routine handles high->low transitions directly to minimize the propagation delay. The power_signal_interrupt is then called which will wake up the chipset task, and low->high transistions continue to be handled in the power state machine. BUG=b:132421681 BRANCH=None TEST=Shorted PP1050_A_PG to ground to force an abrupt power down and then measured time via scope between PG_EC_RSMRST and EC_PCH_RSMRST. The delay is reduced from ~1 msec to 45 uSec. Change-Id: I266138a2e235ce47f3060f8e1f6f9bc6a75073ae Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757267 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* power: Replace weak attr with __overridableYilun Lin2019-08-221-5/+5
| | | | | | | | | | | | | | | | | This CL annotates __overridable to the following functions: board_system_is_idle power_chipset_handle_host_sleep_event power_board_handle_host_sleep_event TEST=make buildall BUG=none BRANCH=none Change-Id: I0168b69c49fab5672238711d4f3a6a5517cdd8b3 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1761759 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* EC: Do not drop SCI events responsible for wake.Ravi Chandra Sadineni2019-08-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC currently clears all events(main copy of hostevents) on every resume. This seems to be added to clear events that are only part of wake mask and not part of SCI mask as they can stick and cause premature wake on next suspend. This patch stops clearing events that are part of SCI mask from the main copy as ACPI subsystem will query and clear them on resume anyway. This helps kernel to identify the reason for wake if it caused by events that are part of SCI mask. Previously coreboot used to depend on main copy to log wake reason. i.e on every resume coreboot used to query and log and clear the wake reason by reading all events from the main copy. Since this also comes in way of kernel in identifying the wake reason, this change also sets up events_copy_b for coreboot by clearing it on every suspend entery. More details can be found at http://go/hostevent-refactor. BUG=b:133262012, b:65976859 BRANCH=None TEST=Tested suspend/resume with wakeup count on hatch and grunt. Change-Id: I0fac250d4dac49af960b29e8b0e28841af2ef509 Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1717498 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Use common code to get power signal's levelVijay Hiremath2019-06-201-6/+1
| | | | | | | | | | | | | | | Removed redundant code in intel_x86 and reusing the common code for getting power signal's level. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I9cd550a2326456189a087459aeb8e6c88a8cad8e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1667647 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* intel_x86: Report S0ix hang detected by EC using console printFurquan Shaikh2019-06-141-0/+1
| | | | | | | | | | | | | | | | | | | | | This change prints out a warning indicating that S0ix hang is detected by EC. This is very helpful when debugging S0ix issues to understand when exactly the EC triggered the wake because of hang detect. BUG=b:134781711 BRANCH=None TEST=Verified on a system stuck before going into S0ix that EC prints out the warning when waking host up because of hang detect. Change-Id: I73c64dc675ed8c4d35ca891fdc5de3e7e8449437 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660014 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Auto-Submit: Furquan Shaikh <furquan@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-22/+2
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power: Manipulate wake mask during s0ix timeoutsEvan Green2019-05-081-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | When S0ix failure detection is enabled and a timeout occurs such that the SLP_S0 line never actually toggles, then s0ix_transition_timeout() sets the HANG_DETECT event bit. This doesn't quite work in this scenario, since the wake mask is only enabled when the power state transitions to S0ix, which happens when the SLP_S0 line toggles. So the AP never sees the event, since it's not in the wake mask and so never causes the EC->AP interrupt line to change. Detect this situation in the timeout function, and explicitly move the wake mask to its S0ix value so that when the event bit is set, (if it is in the wake mask), the system will wake up. Doing this forcefully gets the wake mask out of sync with the power state. So upon resume, explicitly restore the wake mask to its S0 state. BUG=b:131434497 BRANCH=none TEST=suspend_stress_test -c1 --suspend_min=60 with a firmware where S0ix fails. Change-Id: Id2e67c6933a7895fba85ccfdff9b336629eabf24 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592469 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power/intel_x86: Introduce s0ix failure detectionEvan Green2019-03-281-2/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces logic in the EC that can detect if the host attempted to go into S0ix, but never made it. The host already sends commands indicating its intent to enter S0ix, and the EC has a SLP_S0 line that gets asserted by the AP when it actually enters S0ix. All that's needed to monitor failures is to arm a timer when receiving the S0ix suspend message. If the SLP_S0 pin goes low, then the suspend occurred and the timer is canceled. If the timer expires before SLP_S0 goes low, then the EC wakes the AP up, since it has entered a shallower idle state than intended, and should be alerted to avoid short battery life. The timer is also started when SLP_S0 is deasserted on resume. The SoC comes out of S0ix to perform housekeeping activities unbeknownst to Linux. In cases where housekeeping fails to suspend all the way back down, this timer will wake the AP. Additionally, the number of S0ix transitions is reported on resume. This enabled the AP to analyze the amount of "sleepwalking" that is done, and can complain if it seems to be waking up too often. Design doc at: https://docs.google.com/document/d/1mY-v02KAuOyET3td9s5GnxeUgMiAcD058oLEo57DZpY/edit BUG=b:123716513 BRANCH=None TEST=Test S0ix on hatch with modified code that forces a timeout, use ectool to send messages manually before and after timeout, Hack Linux to fail suspend very late to verify no regressions. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ia64b496675a13dbed4ef74637f51e39eee68aa1a Reviewed-on: https://chromium-review.googlesource.com/1501512 Commit-Ready: Evan Green <evgreen@chromium.org> Tested-by: Evan Green <evgreen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* power/intel_x86: Do not restore SCI/SMI masks if not backed upFurquan Shaikh2019-02-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | Currently, if the host indicates intent to enter S0ix using host command but fails to drop into S0ix (i.e. assert SLP_S0#), then it results in EC not backing up SCI/SMI masks. However, SCI/SMI masks were being unconditionally restored when host sent command to exit S0ix. This resulted in failed S0ix to wipe out the SCI mask. This change skips restoring SCI/SMI masks if backup masks are zero. BUG=b:124540202 BRANCH=None TEST=Ensured that with S0ix failure, SCI mask was not wiped out. Change-Id: Ia79829b616ebff460e2436b03653f74aaf6c1ba0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1476291 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cometlake: Add power sequencing support for cometlake chipsetScott Collyer2019-01-241-0/+2
| | | | | | | | | | | | | | | This CL adds cometlake specific portions of power sequencing. BRANCH=none BUG=b:122251649 TEST=make buildall, verified in factory that AP gets to S0 Change-Id: I84726cd522ab55ca9ec095b94392ffa387fb253f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1377570 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* intel_x86: Clear SCI/SMI masks only after host enters S0ixFurquan Shaikh2018-10-081-42/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CL:1099968 cleared SCI/SMI masks on receiving host command indicating entry into S0ix. On the other hand, wake mask is programmed only after host actually enters S0ix based on the EC power state machine. However, if the host actually takes a long time to suspend, then it leaves a wide window open where none of the masks are programmed and hence user events like lidopen could get dropped. This change updates the behavior to ensure that SCI/SMI masks get cleared only after power state machine actually enters S0ix based on the SLP_S0 signal. This action is not done as part of a suspend hook because other hooks can result into host events getting set that can trigger SCI/SMI thus leading to the original problem of EC not going into low power idle. Hence, SCI/SMI masks are cleared before any suspend hook is run. BUG=b:116540387 BRANCH=nocturne TEST=None Change-Id: I463c12febc49eefe852bd6e2c2535e96ad94ada0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1258564 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* intel_x86: fix the build error when removing CONFIG_POWER_S0IXZhuohao Lee2018-08-091-0/+2
| | | | | | | | | | | | | | | | | | | | | | The ec build error if the CONFIG_POWER_S0IX is removed from board.h This patch fixes the build error: power/intel_x86.c:515:13: error: 'lpc_s0ix_suspend_clear_masks' defined but not used [-Werror=unused-function] static void lpc_s0ix_suspend_clear_masks(void) ^ power/intel_x86.c:529:13: error: 'lpc_s0ix_resume_restore_masks' defined but not used [-Werror=unused-function] static void lpc_s0ix_resume_restore_masks(void) ^ BUG=none BRANCH=master TEST=1. make buildall -j 2. Removing CONFIG_POWER_S0IX from rammus/board.h, build pass Change-Id: I8c533736a7efb9f9f78ff71044431dd8a1698481 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1168271 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* icelake: Add power sequencing support for icelakeScott Collyer2018-07-271-1/+3
| | | | | | | | | | | | | | | | | This CL adds code to support x86 power sequencing for icelake. BRANCH=none CQ-DEPEND=I0bf29d69de471c64f905ee8aa070b15b4f34f2ba BUG=b:111121615,b:111853963 TEST=make buildall. Also tested on P0 and verified that AP gets to S0. Change-Id: I3513f2e598162b2362d56c33df76d16b63864bd3 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123318 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-2/+2
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* reset: Log the reason for AP resets.Jonathan Brandmeyer2018-07-261-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a new EC host command 'uptime info' which gathers up some information which may be useful for debugging spurious resets on the AP (was the EC reset recently? Why was the EC reset? If the EC reset the AP, why did it do so?, etc.). Provide ectool support for the same. Example results of `ectool uptimeinfo`: ``` localhost ~ # ectool uptimeinfo EC uptime: 475.368 seconds AP resets since EC boot: 2 Most recent AP reset causes: 315.903: reset: console command 363.507: reset: keyboard warm reboot EC reset flags at last EC boot: reset-pin | sysjump ``` BRANCH=none TEST=Perform some `apreset` commands from the EC console and observe their side-effects via the `ectool uptimeinfo` command on the AP side. Test sequences include no-resets through 5 resets, observing that the ring buffer handling was correct. BUG=b:110788201, b:79529789 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I0bf29d69de471c64f905ee8aa070b15b4f34f2ba Reviewed-on: https://chromium-review.googlesource.com/1139028 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* host_event: Handle SCI/SMI masks correctly when using S0ixFurquan Shaikh2018-06-151-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When host is using S0ix, BIOS is not involved during suspend or resume paths. Thus, until now, SCI and SMI masks were preserved across S0ix suspend/resume cycles. However, it was identified in b:78497503 that if SCI is generated after host enters S0ix, then it results in EC eSPI controller waiting for host controller to respond to the SCI virtual wire event. This prevents the EC from entering low power idle mode. In order to fix the above issue, this change ensures that SCI and SMI masks are cleared when host expresses its interest to enter S0ix. Since these masks are not re-programmed by the host on resume, EC maintains backup copies of both the masks. On resume from S0ix, backup copies are used to restore the masks for SCI and SMI. This change applies to both eSPI and LPC systems since SCI/SMI should not be generated (physical or virtual) when host is in S0ix. This implementation follows the design proposed in: https://docs.google.com/document/d/1J2VYeVXV-KZnIHvtDyOrcH4AXJipsSX6m8oZIDSdtv8/edit?usp=sharing BUG=b:78497503 BRANCH=None TEST=Verified following: 1. SCI and SMI masks are programmed correctly on boot-up. 2. SCI and SMI masks are set to 0 when host enters S0ix. 3. SCI and SMI masks are restored correctly on S0ix resume. Change-Id: Iaa3981e6545d2d3cff51649642f6926f0d4ec31f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1099968 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power: Add CONFIG_* option for PROCHOT polarity.Aseda Aboagye2018-06-081-0/+7
| | | | | | | | | | | | | | | | | | | The common x86 chipset code assumed that CPU_PROCHOT was active high, however on some boards it's actually active low. This commit simply adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts the places where the signal is used. BUG=b:109882953 BRANCH=poppy TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted by default. Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1092150 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-231-2/+2
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* intel_x86: Get rid of CHIPSET_PRE_INIT hookFurquan Shaikh2018-04-191-3/+0
| | | | | | | | | | | | | | | | | Now that all boards are moved to using chipset_pre_init_callback, get rid of hook notification for CHIPSET_PRE_INIT from x86 power state machine. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018736 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chipset: Add callback for chipset pre-initializationFurquan Shaikh2018-04-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a callback for chipset_pre_init_callback which is made by x86 common power state machine when in G3S5 state. Until now, there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by chipset task when in G3S5 state. However, there are at least following reasons why this should be a callback and not a hook notification: 1. The initialization that is done as part of pre-init could be essential for the power state machine to make progress. Though the chipset task goes to sleep waiting for power signals after the hook notification, pre-initialization can all be done as part of a callback since it is mostly board-specific code that is doing work to initialize PMIC. 2. Typically, boards use I2C transactions to setup PMIC on getting chipset pre-init notification. However, since i2c transfers are not encouraged in hook task, they have to be deferred anyways. 3. Since the initialization is being done as part of hook task, use of any constructs e.g. pwr_5v_en_req which allows multiple consumers to enable/disable power rails will use task id for hook task. Instead it is better to provide correct information about the task by letting chipset task perform this request. Thus, this change adds a callback chipset_pre_init_callback in G3S5 state for x86 power state machine. This callback is guarded by CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK. The hook notification is left as is for now until all x86 boards are moved over to using the newly added callback. BUG=b:78259506 BRANCH=None TEST=None Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018733 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Code cleanup: Remove cold reset logicVijay Hiremath2018-04-031-1/+1
| | | | | | | | | | | | | | | | | | | | | Majority of the chipsets do not have a dedicated GPIO to trigger AP cold reset. Current code either ignores cold reset or does a warm reset instead or have a work around to put AP in S5 and then bring back to S0. In order to avoid the confusion, removed the cold reset logic and only apreset is used hence forth. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually tested on GLKRVP, apreset EC command can reset AP. Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/991052 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-251-0/+31
| | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power: create CONFIG_CHIPSET_GEMINILAKEJett Rink2018-03-201-2/+3
| | | | | | | | | | | | | | | | | | Geminilake uses the same power sequencing code as Apollolake. Instead of the board specifying the wrong chipset, we will make the correct chipset reuse the existing power code. This also gives us flexibility in the future if GLK needs to vary from ALK in any of shared code. BRANCH=none BUG=b:74020444 TEST=build all Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969613 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cleanup: fixing typoJett Rink2018-03-061-1/+1
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I7139fb8e23bd613f2a3ce86057a9210577e74c6c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949723 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* espi: Add API to test if signal is eSPI virtual wireScott Worley2018-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add espi_signal_is_vw in new file common/espi.c for testing if a signal is an eSPI virtual wire. API used in power common and intel_x86. Fix CONFIG_BRINGUP support for eSPI (off by default). Add espi_vw_get_wire_name returning a pointer to constant string. Chip modules do not need to maintain names of eSPI signals. BRANCH=none BUG= TEST=Build poppy and other eSPI enabled boards. Test power state machine. Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/836818 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host_events: Introduce unified host event commandJenny TC2017-12-061-48/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=make buildall -j. And verfieid following scenario 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC(making get_feature_flags1() return 0) Change-Id: Idb82ee87fffb475cd3fa9771bf7a5efda67af616 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/576047 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Commit-Ready: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Auto power-on after battery SOC is above minimum requiredFurquan Shaikh2017-11-281-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | If power-up is inhibited by charger because of battery SOC, then check for the conditions again on BATTERY_SOC_CHANGE. This allows the EC to boot the AP up on connecting AC power and SOC going above the minimum required. BUG=b:65864825 BRANCH=None TEST=Verified following on coral and soraka: 1. Discharge battery to ~0% 2. Connect AC power ==> Power-up is inhibited 3. When battery SOC reaches 1%. AP is not taken out of reset: "[12.974428 Battery 1% / 8h:4 to full] [12.980439 power-up still inhibited]" 4. When battery SOC reaches 2%, AP is taken out of reset: "[9.230148 Battery 2% / 4h:5 to full] [9.236122 Battery SOC ok to boot AP!]" Change-Id: Ifa89f8929987d86c9e02530b663d563dbe25ed85 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753294 Reviewed-by: Shawn N <shawnn@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "power: Get rid of power_board_handle_host_sleep_event"Furquan Shaikh2017-11-151-1/+11
| | | | | | | | | | | | | | | | | This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall Change-Id: I6885e7447277d853a2414be299dfea25f5547df4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771054 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Get rid of power_board_handle_host_sleep_eventFurquan Shaikh2017-10-311-11/+1
| | | | | | | | | | | | | | | | | power_board_handle_host_sleep_event was added to allow boards like poppy to enable/disable PMIC VR decay only once during S0ix entry/exit. Now that the chipset hooks have been fixed, there is no need of this board specific callback. If in the future, there is a need to have such a callback, this change can be reverted. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745982 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Add default sleep event state HOST_SLEEP_EVENT_DEFAULT_RESETFurquan Shaikh2017-10-311-3/+5
| | | | | | | | | | | | | | | | | | Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to reinitialize S0ix flag, add a new default state HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of the code to take correct action depending upon the state that is currently triggered. BUG=None BRANCH=None TEST=Verified that SLP_S0# interrupt doesn't get asserted during runtime S0ix. Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745901 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power/intel_x86: Fix S0ix suspend/resume hook notificationsFurquan Shaikh2017-10-241-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a fundamental difference in host behavior w.r.t. S3 and S0ix. When the host enters S3, it asserts the SLP_S3# signal until it is woken back up. Thus, EC depends on the SLP_S3# signal state to decide when to notify listeners about CHIPSET_SUSPEND and CHIPSET_RESUME state. With S0ix, SLP_S0# signal is asserted whenever host enters S0ix. However, periodically (every 8 seconds), the host wakes up for some bookkeeping activities, but does not come out of the low power mode completely. This bookkeeping activity takes ~2-5 ms and the host goes back into S0ix state. Because of this periodic activity, SLP_S0# signal is de-asserted and asserted back every 8 seconds. Thus, if the power state machine depends solely on the SLP_S0# signal to notify CHIPSET_SUSPEND and CHIPSET_RESUME states, then all the listeners would be performing unnecessary actions every 8 seconds. This leads to a number of side-effects including: 1. Dual-role toggle being enabled and disabled every 8 seconds. 2. Power spikes in EC power consumption during S0ix every 8 seconds. In order to avoid the side-effects of periodic host activity in S0ix, this change adds a new flag s0ix_notify, which is set based on the notifications that are pending based on host sleep event. On receiving host sleep event for S0ix suspend, s0ix_notify will be set to S0IX_NOTIFY_SUSPEND. Next, whenever SLP_S0# is asserted, power_state machine notifies listeners of CHIPSET_SUSPEND and resets s0ix_notify flag to S0IX_NOTIFY_NONE. Thus, all future assertions of SLP_S0# do not result in the suspend notification. Similarly, on resume, power_state machine will not notify CHIPSET_RESUME on SLP_S0# deassertion. Instead the host sleep event for S0ix resume will set s0ix_notify flag to S0IX_NOTIFY_RESUME and wake chipset task. The power state machine in turn will notify listeners of the resume event and reset s0ix_notify flag. BUG=b:65356050,b:67750352 BRANCH=None TEST=Verified that the CHIPSET_SUSPEND/CHIPSET_RESUME notification happens only once during a system suspend/resume cycle. Periodic host wakes for book-keeping activities do not result in CHIPSET_SUSPEND/CHIPSET_RESUME notifications. Change-Id: Idf253b9393a0c25ff2eac63c60ddbcd3af954818 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/729478 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power/intel_x86: Give host a chance to read hostevents on S0ix wakeFurquan Shaikh2017-10-191-6/+5
| | | | | | | | | | | | | | | | | Instead of clearing out all the host events on S0ix wake, provide an opportunity to the host to read the events and log it. Move the call to clear events to the point where host sends a command indicating exit from S0ix. BUG=b:67874513 BRANCH=None TEST=make -j buildall. Verified that host events are cleared by the host during logging. Change-Id: I339dc70d761bb851286d98c5c20094ccaefd238f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/724188 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exitFurquan Shaikh2017-10-031-0/+7
| | | | | | | | | | | | | | | | | | | Runtime S0ix results in SLP_S0 signal being toggled continuously resulting in an interrupt storm on the EC. In order to avoid this, enable SLP_S0 power signal only when host indicates intent to enter S0ix and disable when host exits from S0ix. BUG=b:65421825 BRANCH=None TEST=Verified that runtime S0ix no longer results in interrupt storm on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0 using powerindebug. Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fizz: Initialize PMIC after AP power is readyDaisuke Nojiri2017-09-291-11/+9
| | | | | | | | | | | | | | | | | On proto3, PMIC isn't powered on POR, thus board_pmic_init fails. With this change, EC waits until AP power is ready before it notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized. When AP power is ready, PMIC should be ready as well. BUG=b:65839247,b:64944394 BRANCH=none TEST=Run reboot [/cold/ap-off] command on BJ and Type-C. Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b Reviewed-on: https://chromium-review.googlesource.com/672152 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Provide chipset and board callbacks on host sleep event commandFurquan Shaikh2017-09-221-0/+15
| | | | | | | | | | | | | | | | This change allows chipset and board to perform any action when host indicates intention to enter sleep state. Chipset can take action like enable/disable power signal interrupts and boards can enable/disable decay of VRs on host intent to enter/exit S0ix. BUG=b:65732924 BRANCH=None TEST=make -j buildall Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/677498 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-1/+1
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* S0ix: use both SLP_S0 interrupt and host command for s0ixJenny TC2017-07-241-12/+25
| | | | | | | | | | | | | | | | | | | | | | | | EC currently uses a host command from kernel to enter s0ix. This patch waits for the SLP_S0 interrupt to come after receiving the host command before entering S0ix. On the exit path, the SLP_S0 interrupt directly triggers the exit rather than waiting for the host command. BRANCH=none BUG=b:37443151 TEST=check in EC logs for SLP_S0 entry and powerindebug output, check suspend_stress_test on reef and soraka works fine, make -j8 buildall runs fine Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2 Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/513705 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* vboot: Jump to RW earlyDaisuke Nojiri2017-07-141-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes EC run vboot in the HOOK task. The vboot routine requires battery and charger info. It waits in a deferred call loop until the charge manager is initialized. BUG=b:63586051 BRANCH=none TEST=Verify the following cases: A. Hardware reboot (type-c/BJ) 1. Unplug AC in S0 then plug in AC: BOOT/BOOT 2. Unplug AC in S5 then plug in AC: S5/S5 3. Unplug AC after A.2 then plug in AC: S5/S5 4. Press PB in S5: BOOT/BOOT B. Software reboot (type-c/BJ) 1. Run EC reboot command in S0: BOOT/BOOT 2. Run EC reboot command in S5: BOOT/BOOT 3. Run EC reboot ap-off command in S0: S5/S5 4. Run EC reboot ap-off command in S5: S5/S5 5. Run host reboot command: BOOT/BOOT 6. Run host shutdown command: S5/S5 C. Recovery tests 1. Press RB and PB in S0: FAIL(*1)/PASS 2. Press RB and PB in S5: FAIL(*1)/PASS(*2) 3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS 4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2) *1: b:63668669 *2: b:63669512. Requires one more PB press. Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568699 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Move common code under common/vbootDaisuke Nojiri2017-07-131-1/+1
| | | | | | | | | | | | | | | This patch moves the code which can be shared with other data verification schemes (e.g. RWSIG) under common/vboot. It also adds unit tests for it. BUG=b:38462249 BRANCH=none TEST=make run-vboot. Verify verification succeeds on Fizz. Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/563463 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power: Add Cannonlake chipset support.Aseda Aboagye2017-07-111-1/+3
| | | | | | | | | | | | | BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564798 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot: Add vboot for EC by ECDaisuke Nojiri2017-06-281-1/+18
| | | | | | | | | | | | | | | | | This patch adds vboot for EC by EC (vboot EC) for x86 systems. When ec is transitioning s5->s3, it checks the power supply is enough to boot AP or not. If not, it runs other checks and may finally validate and jump to a RW image. BUG=b:38462249 BRANCH=none TEST=Boot Fizz on barrel jack and type-c charger. Change-Id: I5988b0595976370c5303c45541702ae89d86fc97 Reviewed-on: https://chromium-review.googlesource.com/518254 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fizz: Set up charge suppliers at bootDaisuke Nojiri2017-05-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Fizz has two power sources: barrel jack and type-c port. It selects a power source at boot and does not dynamicall switch to the other ports after that. Fizz initializes all power suppliers of all ports to zero then initialize the source supplier (barrel jack or type-c port). When both sources are provided, it prefers a barrel jack. This detection is done by reading the voltage on PPVAR_PWR_IN. If barrel jack is detected as a sink, type-c port works as a source only. If type-c port is detected as a sink, type-c port works as a sink only. Fizz does not have a battery. So, battery module is removed. BUG=b:37573548,b:37316498 BRANCH=none TEST=Boot on both type-c & barrel jack. Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/499547
* Allow lid-less configurationDaisuke Nojiri2017-05-091-4/+0
| | | | | | | | | | | | | | | | | | | power_button_x86.c and switch.c assume there is a lid switch. This patch separate them so that a board with power button but with no lid can be configured properly. This patch also moves backlight control to the board directory so that only the boards with a backlight turn it on/off when power state changes. BUG=none BRANCH=none TEST=boot fizz. make buildall. Change-Id: If4070cdc4b1221fae68b35ec3497335d81f192fd Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/489602 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power/intel_x86: add tablet switch event wake masksArchana Patni2017-05-021-8/+10
| | | | | | | | | | | | | | | | | | | | | The wake mask programming for S0ix is done in EC. This patch adds handling for the tablet switch events in the S0ix flows. BRANCH=none BUG=b:37223093 TEST=attach or detach base and check if event is generated Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Change-Id: Ibd53e85d5a3a1b776e519b70860404684c9ab0fb Reviewed-on: https://chromium-review.googlesource.com/486462 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Handle unexpected power loss in S0iXVijay Hiremath2017-01-211-4/+12
| | | | | | | | | | | | | | | | | | Picked the code from Glados branch. Change-Id: I0f24f717f712dcd46e3ddca2a8c86888739f3deb Reviewed-on: https://chromium-review.googlesource.com/390343 BUG=chrome-os-partner:61645 BRANCH=none TEST=Manually tested on Reef. Reef exits from S0iX upon issuing 'apreset warm' & 'apreset cold' from the ec console. Change-Id: Ie5fa4ad79b7c78344e99fcbf4ba2b5b800f9934c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427393 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel_x86: Handle RSMRST signal in Intel x86 common codeVijay Hiremath2017-01-211-18/+55
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427018 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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