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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I55993b8007f621b6a78398b863199fb90b1832a7
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727062
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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PCH_PWROK signal is combination of ALL_SYS_PWRGD and SLP_S3. Silego
chip used on MTL-RVP can detect the high voltage level at 2.13V.
However SLP_S3 coming from PCH is 1.8V. Hence use the EC gpio to
trigger the PCH_PWROK.
BUG=none
BRANCH=none
TEST=MTL-RVP can boot to S0
Change-Id: I9a9d12f8d26452db5b446776d8b7c61c84918227
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3585883
Reviewed-by: Keith Short <keithshort@chromium.org>
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Added base code for Meteorlake power sequencing. Implementation closely
follows Intel Icelake power sequencing as reference and modified the
logic based on Meteorlake Platform Development Guide.
BUG=b:223985632
BRANCH=none
TEST=Able to boot MTLRVP to S0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Change-Id: Ia551a1e226c648d9f23aff05ad3d44c3735a2495
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516600
Reviewed-by: Keith Short <keithshort@chromium.org>
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