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* power: move headers to include/powerJack Rosenthal2020-12-031-1/+1
| | | | | | | | | | | | | | This makes the headers visible to the Zephyr build. BUG=b:173798264 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* EFS2: Implement Early Firmware Selection ver.2Daisuke Nojiri2020-02-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring the benefts to Chromebooks, which are: - Reduce RO dependency and presence. Allow more code to be updated in the fields. - Remove jumptag and workarounds needed for late sysjump. Major imporvements over v1 are: - No A/B slot required. - No signature in RW or public key in RO. - Rollback-attack protection. - Verifies only RW being used instead of whole RW section. For battery-equipped devices, additional benefts are: - Immediate boot on drained battery. - Support recovery mode regardless of battery condition. - Faster charge in S5/G3. EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm). EFS2 is documented in go/ec-efs2. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1045217,chromium:141143112 BRANCH=none TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode. TEST=Wake up EC from hibernate. TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep. Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-3/+4
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-131-1/+37
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* reset: Log the reason for AP resets.Jonathan Brandmeyer2018-07-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provides a new EC host command 'uptime info' which gathers up some information which may be useful for debugging spurious resets on the AP (was the EC reset recently? Why was the EC reset? If the EC reset the AP, why did it do so?, etc.). Provide ectool support for the same. Example results of `ectool uptimeinfo`: ``` localhost ~ # ectool uptimeinfo EC uptime: 475.368 seconds AP resets since EC boot: 2 Most recent AP reset causes: 315.903: reset: console command 363.507: reset: keyboard warm reboot EC reset flags at last EC boot: reset-pin | sysjump ``` BRANCH=none TEST=Perform some `apreset` commands from the EC console and observe their side-effects via the `ectool uptimeinfo` command on the AP side. Test sequences include no-resets through 5 resets, observing that the ring buffer handling was correct. BUG=b:110788201, b:79529789 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I0bf29d69de471c64f905ee8aa070b15b4f34f2ba Reviewed-on: https://chromium-review.googlesource.com/1139028 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-251-18/+0
| | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Fizz: Execute PMIC reset before vboot_mainDaisuke Nojiri2018-02-081-1/+3
| | | | | | | | | | | | | | | | | | | When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* skylake: Check for hard and soft off in chipset_force_shutdownFurquan Shaikh2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | Intention of chipset_force_shutdown is to power off the AP by simulating power button press until it results in power button override and shuts down AP. However, if AP is already in hard or soft off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already off, and simulating power button press results in charge_prevent_power_on from incorrectly assuming that the power button is pressed by user. Thus, check if the system is in soft or hard off before shutting it down. BUG=b:65864825 BRANCH=None TEST=Verified that apshutdown still works fine from EC console on soraka. Change-Id: Id892e5b2c8c1e4ce0bad95a70ea6a3ed547a7047 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/774298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Use SYS_RESET signal to trigger warm and cold resetFurquan Shaikh2017-07-181-23/+12
| | | | | | | | | | | | | | | | RCIN# signal is known to not work properly for performing a warm reset when the CPU is in a bad state. This results in the common key combo (Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET signal instead to trigger both cold and warm chipset reset. BUG=chromium:721853 BRANCH=None TEST=make -j buildall Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575947 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* power/skylake: Ensure panic data is backed up before PMIC resetFurquan Shaikh2017-06-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On PMIC reset, VCC power rail goes down thus resulting in loss of panic data. Thus, provide a chance to the chip to backup panic data if available. BUG=b:62076222 BRANCH=None TEST=make -j buildall 1. > crash divzero > panic === PROCESS EXCEPTION: 06 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :00000001 r5 :00000000 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : Divide by 0 mmfs = 2000000, shcsr = 0, hfsr = 0, dfsr = 0 2. > crash assert > panic === PROCESS EXCEPTION: 00 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :dead6663 r5 :000000a4 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0 3. > crash watchdog > panic === PROCESS EXCEPTION: 3c ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :dead6664 r5 :0000000a r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0 4. > crash unaligned > panic === PROCESS EXCEPTION: 06 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :200c0d9e r5 :00000000 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : Unaligned mmfs = 1000000, shcsr = 0, hfsr = 0, dfsr = 0 Change-Id: Ife5c9bbc12dcf6c4922f18b7530b21a3b87e65b3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/530138
* skylake: Add workaround for boards that cannot save reset flagsDuncan Laurie2017-05-251-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some hardware has an issue where the reset flags are lost on power cycle because the EC backup ram loses power. This causes the flag to not power on the AP (ap-off) to be lost. In order to pass FAFT it is required that boards support this flag, so this commit adds a workaround where the skylake chipset code will call into the board to ask if it has working reset flags and if not it will skip the PMIC reset if the "ap-off" flag has been set. The "ap-off" flag is purely for testing, it is not possible for users to do this without having access to the EC console. (which is currently not possible at all with CCD unless you can also build a debug cr50 image) BUG=b:38187362,b:35585876 BRANCH=none TEST=manual testing on Eve: execute 'reboot ap-off' and ensure that the AP does not power on. Also ensure that 'dut-control power_state:rec' works as expected and does not power off at the recovery screen due to a power button press. Change-Id: If11e17179e9173509b9a6ae1ef0d94a50ba181d0 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/514503 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power/skylake: Use power_get_signals instead of power_has_signalsFurquan Shaikh2017-02-181-1/+2
| | | | | | | | | | | | | | | | | In chipset_handle_espi_reset_assert, check the state of SLP_SUS# signal using power_get_signals instead of power_has_signals since we do not care if the check fails. This avoids unwanted "power lost input" prints on the EC console. BUG=chrome-os-partner:63033 BRANCH=None TEST=Verified that entry into S3 does not result in any "power lost input" messages on EC console. Change-Id: I88bc76a90b48e7c565423235f6e8431176ed4872 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444262 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* chip/npcx/espi: Handle global reset events asserting eSPI_Reset#Furquan Shaikh2017-02-091-0/+14
| | | | | | | | | | | | | | | | | | | | | | In case there is a sudden power loss to PCH, then there are no eSPI VW messages sent from the PCH to EC indicating power state transition into S5. Instead, the eSPI compatibility spec defines such events as global reset events. For global reset events, eSPI_Reset# signal is asserted without SLP_SUS# being asserted. This acts as an indication to the EC that there was a global reset event. Add a callback chipset_handle_espi_reset_assert that takes any necessary action whenever eSPI_Reset# pin is asserted. On skylake, it would check if power button was being pressed and release the button. BUG=chrome-os-partner:62014 BRANCH=None TEST=Verified that apshutdown works as expected. Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438935 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power/skylake: Add option to reset pmic using LDO_ENFurquan Shaikh2017-01-231-0/+37
| | | | | | | | | | | | | | | | | Add a config option that can be used by chipset to provide PMIC reset using LDO_EN. This is required for ensuring that the AP is power cycled properly. Implement the special pmic reset for skylake chipsets. BUG=chrome-os-partner:61883 BRANCH=None TEST=Verified that reboot on EC console resets the AP and does not get stuck in G3 on poppy. Change-Id: I5f680fede5cb4effa86243f51edfdea09db4d975 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/431192 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* intel_x86: Handle RSMRST signal in Intel x86 common codeVijay Hiremath2017-01-211-29/+1
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: Iddd16cba5f1dc62341dfbc8568b490439b7d593b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/427018 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Group Intel x86 power sequencing common codeVijay Hiremath2017-01-201-257/+11
| | | | | | | | | | | | | | | | | | | Grouping the Intel x86 power sequencing common code so that the future chipset power sequencing implementation can make use of the existing code. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Manually tested on Reef & Chell. System can boot to OS. S3, S5, hibernate are working. Change-Id: I29dc208eacb3db47c640d028e9551ab3d8d4288c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/402272 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Extract Intel x86 power sequencing common codeVijay Hiremath2017-01-071-89/+8
| | | | | | | | | | | | | | | | | Extracted Intel x86 power sequencing common code from skylake.c and apollolake.c to implement common code for power sequencing. BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Reef can boot to OS. S3, S5, hibernate are working. Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/406486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Reuse the sleep event code from the common codeVijay Hiremath2017-01-061-51/+6
| | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=make buildall -j Change-Id: I881b92215f24ea047ec4fc3109b174ff1615de29 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/425486 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Add support to S0iX based on host commands from KernelVijay Hiremath2016-11-131-54/+53
| | | | | | | | | | | | | | | | | | Picked the code from Glados branch. Change-Id: I4bf114235c4d542dd7cf0dad6427c771e54d4611 https://chromium-review.googlesource.com/#/c/331358/ BUG=chrome-os-partner:59742 BRANCH=none TEST=make buildall -j Change-Id: Ib79f1209dfd9e6a9de0438cb1866bba2939e5393 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/410036 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* lpc: Add function for host reset without RCIN GPIODuncan Laurie2016-10-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Prior x86 boards have had GPIO for toggling RCIN directly on the PCH, although many likely had HW-assisted methods as well. With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality software control over RCIN Virtual Wire is not available with the npcx EC, so the legacy LPC interface for pulsing KBRST must be used instead as this is the only way to generate RCIN. This method will likely vary on different EC chips, but for skylake it can just be abstracted into the LPC module. BUG=chrome-os-partner:58666 BRANCH=none TEST=successful 'apreset warm' on eve EC console Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400037 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add board callback before RSMRST# state changeDuncan Laurie2016-10-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | This board function allows workarounds to be applied to a board after all power rails are up but before the AP is out of reset. Most workarounds for power sequencing can go in board init hooks, but for devices where the power sequencing is driven by external PMIC the EC may not get interrupts in time to handle workarounds. For x86 platforms and boards which support RSMRST# passthrough this board callback will allow workarounds to be applied despite the PMIC sequencing by ensuring that the function is executed before RSMRST# deassertion. BUG=chrome-os-partner:58666 BRANCH=none TEST=test IMVP8 workaround on multiple eve boards Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/402591 Reviewed-by: Shawn N <shawnn@chromium.org>
* include: Add default state for ESPI and VW_SIGNALSDuncan Laurie2016-10-251-1/+1
| | | | | | | | | | | | | | Add the default undefined state for CONFIG_ESPI and rename CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS. BUG=chrome-os-partner:58666 BRANCH=none TEST=pass presubmit checks Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400032 Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add virtual-wire power signals support for skylake.Mulin Chao2016-08-131-6/+33
| | | | | | | | | | | | | | | | | | | Add virtual wire power signals support for skylake. By adding CONFIG_VW_SIGNALS definition in board level driver, we can save three GPIOs (SLP_S3/SLP_S4/CLK_RUN) on skylake platform. Modified sources: 1. common.c: Add support for VW power signals. 2. skylake.c: Add upper func to get system sleep state through GPIOs or VWs. BRANCH=none BUG=none TEST=make buildall; test boot up and shut down on eSPI POC of wheatley. Change-Id: I0eae363dad8cec011eb32929a40701f19fde7e1a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366711 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* chell: pmic: Delay disable of V0.85AShawn Nematbakhsh2016-04-121-2/+7
| | | | | | | | | | | | | | | | | | | Various voltage rails will be enabled / disabled by the PMIC when GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A by approximately 25ms in order to allow V1.00A to sufficiently discharge first. BUG=chrome-os-partner:52047 TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges faster than V0.85A. BRANCH=glados Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337325 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* kunimitsu: hibernate: enable PseudoG3 support at board levelKevin K Wong2016-02-181-19/+0
| | | | | | | | | | | | | | this is to move the existing code from chipset level to board level since PseudoG3 is a board feature that required specific hardware. BUG=none BRANCH=glados TEST=use hibernate command to enter PseudoG3 Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327677 Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: set and clear wake masks in S0 <-> S0ix transitionsArchana Patni2016-02-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the wake masks when the SMI is invoked. For S0ix, EC sets and clears the wake mask via this patch. These functions are directly invoked from the state machine transition states. During S0ix entry, the wake mask for lid open is enabled. During S0ix exit, the wake mask for lid open is cleared. All pending events are also cleared BRANCH=none BUG=chrome-os-partner:48834 TEST=test lidopen in S0ix Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f Reviewed-on: https://chromium-review.googlesource.com/320190 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Better handling of S0->S5->S0 pathDuncan Laurie2016-01-221-2/+1
| | | | | | | | | | | | | | | | | If we are doing a cold reset or if Deep S5 is disabled we will go into S5 and need to be able to power up again, but we do not have enough information to know what direction the sequencing may go from S5 (to G3 or up to S0). So limit the RTCRST check to just the explicit G3->S5 path and let the normal checking of SLP_S4 signal happen otherwise. BUG=chrome-os-partner:49564 BRANCH=glados TEST=pass FAFT testing finally Change-Id: I202234e58281e6b007ad2b98396994222d0831b2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/323087 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Fix for RTCRST check in S5 power down pathDuncan Laurie2016-01-211-1/+5
| | | | | | | | | | | | | | | | | | | | | The power state machine goes through POWER_S5 state both when sequencing up and down, but we only should check for it to time out on the way up. In order to know what direction it is going add a variable to indicate the direction. On samus where this was done before it did not go through POWER_S5 on the way down, instead going directly to POWER_S5G3 so I did not run into this same issue. BUG=chrome-os-partner:49564 BRANCH=glados TEST=successfully power down without the EC thinking it is timing out and trying to reset RTC. Change-Id: I1f53f3a252bdc2ec8c656e30b3de7f98aaa661a0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322898 Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Add support for asserting RTCRST if power sequencing failsDuncan Laurie2016-01-201-32/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pulse RTC reset to the PCH when power sequencing exit fails we need to watch for SLP_S4 to deassert and if it does not then assert RTCRST using a board specific method. This is attempted up to 5 times before giving up and staying in G3. On skylake the RSMRST passthru needs to be honored when the task is woken up, so while waiting call handle_rsmrst() if woken up early. This is needed because it is RSMRST that actually tells the PCH to try and wake. This is all wrapped in a config option and board specific method because not all boards have a GPIO to control RTCRST and if they do they may not all use the same method to assert it. BUG=chrome-os-partner:49564 BRANCH=glados TEST=manually tested on chell EVT: First, ensure board sequences properly if everything is OK for a normal boot. Next, modify handle_rsmrst() to not pass through the signal in order to simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST and power up again 5 times before giving up and staying in G3. Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322724 Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: Change unlocked battery level ignore conditionsShawn Nematbakhsh2016-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | x86 systems will auto-power-on when power is applied to the EC. When the battery level is critically low, power-on is prevented, except when the system is unlocked. So, when unlocked, some systems will auto-power-on regardless of battery level, overcurrent the charger / battery, and then repeat forever. Prevent this reboot loop by ignoring auto-power-up when the battery is critically low, regardless of system unlocked status. BUG=chrome-os-partner:48339 TEST=Verify power-up is prevented on no-battery chell w/ donette. Then, run 'powerbtn' on EC console and verify system powers on (and overcurrents). BRANCH=None Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319187 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: increase retry count in power upli feng2015-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | During power up, system will wait at most CHARGER_INITIALIZED_TRIES delay to check if battery percentage or negociated charger power can meet minimum requirement. In some cases, it takes longer time(observed negotiated to min power took 2 seconds). So increase CHARGER_INITIALIZED_TRIES from 10 to 40 to give total 4 seconds delay. BUG=chrome-os-partner:48339 BRANCH=none TEST=Verified in Kunimitsu system, negotiation to 5V@3A is done within retry/delay. Change-Id: I18c5fc676076f8d37d0a5360543f54aa85f48f77 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/318652 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: fix retry counter checking in power upli feng2015-12-161-1/+1
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=`make buildall -j` Change-Id: If015f655c4ccaba147fb886452d5fe756ec54425 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/317644 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: remove fab 3 related changesKevin K Wong2015-11-261-12/+1
| | | | | | | | | | | BUG=chrome-os-partner:44704 BRANCH=none TEST=verified image can boot on kunimitsu fab 4 Change-Id: If5f48bdd5dee5998fec2c079ee46f34cb604fd38 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/314126 Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu: Add S0ix on SLP_S0 assertionKyoung Kim2015-11-191-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep and EC is eligable to enter heavy sleep idle task. Wakeup from S0ix by lid open, any key press, power button or track pad will be done by PCH block by asserting SLP_S0. At S0ix, 1 msec pulse will be generated every 8sec and this signal should be ignored since this is NOT S0ix entry/exit related and defered interrupt for SLP_S0 were added. BRANCH=master BUG=none TEST=in OS shell, run following commands. Following command is valid with coreboot with S0ix patches. "echo freeze > /sys/power/state" then, Measure EC power consumption and compare it with one in S0. And on EC console, there should be NO periodic message, "power state 4 = S0ix, in 0x001d" every 8 sec. Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307947 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Move USB enable gpio control to board hooksDuncan Laurie2015-10-121-7/+0
| | | | | | | | | | | | | | | Some boards may not have a USB2_ENABLE GPIO so we need each board to do the USB power enable/disable in a board hook. BUG=chrome-os-partner:46289 BRANCH=none TEST=make -j buildall Change-Id: I830cbaf41c118b2f74e23fa946a4187f6293a7d5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/304397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Kunimitsu: Enable support for limiting the inrush currentVijay Hiremath2015-09-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | Enable the support for limiting the inrush current by routing the PCH_SLP_SUS through EC gpio PMIC_SLP_SUS which allows the DUT to boot on charger without the battery / dead battery. This is applicable to Kunimitsu FAB4 only. Enabling the Glados patch for Kunimitsu FAB4. Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13 Reviewed-on: https://chromium-review.googlesource.com/287378 BUG=chrome-os-partner:44706 TEST=FAB4 prototype boots to UI without battery / dead battery. BRANCH=none Change-Id: Ie81cdf3c59fc02d6d59dd06ca321705ca06e7b88 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/296521 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: allow power button power ons in S5 after apshutdownAaron Durbin2015-08-311-3/+3
| | | | | | | | | | | | | | | | | | | On skylake the apshutdown command holds the power button asserted until the power state machine decides to deassert the power button. Previously this check was taking place in G3 state. As such when the board waited in S5 for 10 secs one couldn't re-power on the system. To alleviate that move the logic for power button deassertion into the S5 state. BUG=chrome-os-partner:44532 BRANCH=None TEST=Used apshutdown. When device got to S5 power noted another powerb command would bring the system back up instead of waiting to enter G3 power state. Change-Id: I9989b27bd48819d7c3e5efd071b0327c38fe91e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295198 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* glados: Disable keyboard + trackpad in tablet modeShawn Nematbakhsh2015-08-241-3/+1
| | | | | | | | | | | | | | | | The internal keyboard and trackpad must be disabled in tablet mode to prevent unwanted input. BUG=chrome-os-partner:44305,chrome-os-partner:40849 TEST=Manual on Glados. Boot system with lid open, verify that keyboard is functional and ENABLE_TRACKPAD is high. Swing lid to tablet mode, verify that keyboard is not functional and ENABLE_TRACKPAD is low. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9f250ae82963c8b497de991b6cce52c86841d08a Reviewed-on: https://chromium-review.googlesource.com/295206 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Skylake: Add low power Pseudo G3 supportVijay Hiremath2015-08-211-3/+19
| | | | | | | | | | | | | BUG=none TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu. With only battery after 1 hour, device enters to Pseudo G3 and the V3p3A is off. With AC connected, device is in G3. BRANCH=none Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/292976 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: power sequencing updateAaron Durbin2015-08-191-36/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number issues with the current skylake power sequencing. First, SLP_SUS_L was not being honored from the chipset when a deep S5 or S3 was requested. Additionally the BATLOW_L signal was being used to block the chipset from waking which caused a race in waking from deep S5 that required an additional pulse of the PCH_WAKE_L signal instead of the chipset seeing the power button event. Another issue is that POWER_S5 state was being completely bypassed so any global resets that brought down SLP_S4_L caused the state machine to enter into G3 state. The code was changed to remove BATLOW_L usage, PCH_WAKE_L in the POWER_G3S5 state, and SLP_SUS_L is honored in the non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L pass-thru to work on glaods. Lastly the code was reorganized to accomodate the above change without sprinkling them throughout the state transitions. BUG=chrome-os-partner:44081 BUG=chrome-os-partner:44082 BUG=chrome-os-partner:43475 BRANCH=None TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh flash plus a global reset doesn't bring the system down to G3. Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293844 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: Wake from Deep S5 after battery low is deassertedstabilize-7374.BDuncan Laurie2015-08-171-7/+16
| | | | | | | | | | | | | | | The system will not wake from Deep S5 if BATLOW# is asserted, so wait for that to deassert, then pulse the wake pin and wait for SLP_SUS_L to deassert. BUG=chrome-os-partner:43545,chrome-os-partner:44079 BRANCH=none TEST=verified on P2 board Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293595 Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: Switch to V2 boardShawn Nematbakhsh2015-08-141-3/+7
| | | | | | | | | | | | | Switch to V2 glados as the default, and remove support for V1. BUG=chrome-os-partner:43075 TEST=`make buildall -j` BRANCH=None Change-Id: I58f33225177d259916e8877084c2c431922e7bc5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: Inhibit AP power-on until charge current limit is setShawn Nematbakhsh2015-08-011-0/+24
| | | | | | | | | | | | | | | | | | Inhibit AP power-on through the BATLOW pin, even if the system is unprotected, until our charger and current limit are initialized. Note that this feature is only functional on glados v2 since other skylake boards do not have BATLOW connected. BUG=chrome-os-partner:41258 TEST=Manual on glados v1 with rework. Remove battery and attach Zinger. Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP boots. Remove all power and attach battery, verify that EC powers on and AP boots. Also verify compilation on glados v2. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13 Reviewed-on: https://chromium-review.googlesource.com/287378
* glados: V2 Board ChangesShawn Nematbakhsh2015-07-241-0/+11
| | | | | | | | | | | | | | | Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2, which is not defined by default in order to support existing boards. BUG=chrome-os-partner:42933 TEST=Verify that Glados v1 board continues to boot AP. Verify compilation on GLADOS_BOARD_V2. BRANCH=None Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287291 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Skylake: Add G3 sleep mode supportVijay Hiremath2015-07-211-0/+3
| | | | | | | | | | | | | BUG=none TEST=Enabled the config and tested on Kunimitsu. Enter "shutdown -h now" form the Kernel console. Device goes to Sleep mode in G3 and charger LED turns off. BRANCH=none Change-Id: I962018dcfac2998ee0a11784adeceb09931b930d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/286781 Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Disable power rails and components when appropriateShawn Nematbakhsh2015-07-151-1/+9
| | | | | | | | | | | | | | | | | - Disable USB, wireless and audio power rail when powering down from S3 - Disable sensor power rail and display backlight when powering down from S0 BUG=chrome-os-partner:42104 TEST=Manual on Glados. Boot AP, verify that display backlight and USB are functional. BRANCH=None Change-Id: I2879f57db555753b280e785df3d2cc967c152f21 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/285545 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* power: skylake: Delay 10ms before deasserting PCH_RSMRST_Lstabilize-7199.BShawn Nematbakhsh2015-06-201-1/+17
| | | | | | | | | | | | | | | According to spec, RSMRST shouldn't be deasserted until 10ms after power signals become active. BUG=chrome-os-partner:41556 TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to G3 on apshutdown, and back to S0 on powerbtn. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4 Reviewed-on: https://chromium-review.googlesource.com/280571 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: Properly handle apshutdown when AP is already shutdownShawn Nematbakhsh2015-06-131-2/+4
| | | | | | | | | | | | | | | | If the AP is already shutdown, apshutdown would previously power the AP up with a power press. Fix this by making sure we're not already in G3 before triggering the power press. BUG=chrome-os-partner:40677 TEST=Run 'apshutdown' on glados while in G3, verify that AP does not power up. BRANCH=None Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277400 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* skylake: Use a simulated power button press to force-shutdown the APShawn Nematbakhsh2015-06-041-2/+13
| | | | | | | | | | | | | | | | Holding the power button is currently the best known way to bring the AP back to a state where it is shutdown and not powered. BUG=chrome-os-partner:40826, chrome-os-partner:40677 TEST=Run `apshutdown` on glados, verify that power state machine transitions to G3 after several seconds. Run `powerbtn`, verify that state machine transitions back to S0. BRANCH=None Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275060 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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