| Commit message (Collapse) | Author | Age | Files | Lines |
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According to spec, RSMRST shouldn't be deasserted until 10ms after power
signals become active.
BUG=chrome-os-partner:41556
TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to
G3 on apshutdown, and back to S0 on powerbtn.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4
Reviewed-on: https://chromium-review.googlesource.com/280571
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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If the AP is already shutdown, apshutdown would previously power the AP
up with a power press. Fix this by making sure we're not already in G3
before triggering the power press.
BUG=chrome-os-partner:40677
TEST=Run 'apshutdown' on glados while in G3, verify that AP does not
power up.
BRANCH=None
Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277400
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Holding the power button is currently the best known way to bring the AP
back to a state where it is shutdown and not powered.
BUG=chrome-os-partner:40826, chrome-os-partner:40677
TEST=Run `apshutdown` on glados, verify that power state machine transitions
to G3 after several seconds. Run `powerbtn`, verify that state machine
transitions back to S0.
BRANCH=None
Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/275060
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change is necessary to ensure power-up of edge-case Skylake parts.
BUG=chrome-os-partner:40677
TEST=Manual on Glados. Boot system to S0, run "i2cxfer r 4 0x60 0x38",
verify that 0x7a is read.
BRANCH=None
Change-Id: Id9e62731aaa75fb2357a05d898ba2d4d28f87d9e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274114
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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PCH_SLP_SUS_L can take up to 29ms to be deasserted after power-on or
RTC reset.
BUG=chrome-os-partner:40677
BRANCH=None
TEST=Manual on glados. Power board, verify that state machine
transitions to S0. Run "reboot" on EC console, verify that state machine
again transitions to S0.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3f6e89eee1190a3fe84fdc7d939c05dfe5b94953
Reviewed-on: https://chromium-review.googlesource.com/274077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Always enable these signals to help debug power sequencing. We'll need
to revert this change later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: Ia845532fe7aed71bcb42b4ca6a9bfa20aa9e3e00
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273900
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change will help us to debug power sequencing and will likely need
to be reverted later.
BUG=chrome-os-partner:40677
BRANCH=none
TEST=sequence to S0 on glados and stay there
Change-Id: I85d1f0f97a3c93cf26c766a749feb23f9cf4ac62
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273680
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Debounce time for the GPIO SYS_RESET_L is 16ms hence increased the time
delay between SYS_RESET_L pin toggling to 20ms.
BUG=chrome-os-partner:40246
TEST=Tested "apreset cold" EC console command on Kunimitsu
BRANCH=none
Change-Id: If17229ce485de708b550ec84939e2696e451cb0c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/270776
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=chrome-os-partner:39510
TEST=Compile Only
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If470b00fec56db0884dbd4c9974140951fc214fd
Reviewed-on: https://chromium-review.googlesource.com/268780
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Add power sequencing for Skylake, following the IMVP8 / ROP PMIC design
for SKL-U / SKL-Y.
BUG=chrome-os-partner:39510
TEST=Compile only
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibf6a0e4415544b6b4b2cf28c167106ce4bfdc54e
Reviewed-on: https://chromium-review.googlesource.com/269460
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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