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* Kahlee: Provide functionality for apshutdownAkshu Agrawal2017-09-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trigger the power press for shutdown. Also, avoid powering up the AP by checking if we are not in G3, before triggering the power press. BUG=b:66698593 TEST= > apshutdown [7045.198370 chipset_force_shutdown()] [7045.198870 PB PCH force press] [7045.199368 PB PCH pwrbtn=LOW] > LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c] [7049.218718 Pass through VGATE: 0] [7049.219281 power state 7 = S0->S3, in 0x000c] [7049.220647 chipset -> S3] [7049.221108 power state 2 = S3, in 0x000c] [7049.221763 power state 8 = S3->S5, in 0x000c] [7049.222522 USB charge p0 m0] [7049.223217 chipset -> S5] [7049.223716 power state 1 = S5, in 0x000c] [7049.224334 PB PCH force release] [7049.224840 PB PCH pwrbtn=HIGH] [7049.232875 SW 0x01] [7049.240557 TCPC p1 Low Power Mode] [7049.252249 TCPC p1 Low Power Mode] [7049.254363 TCPC p0 Low Power Mode] [7049.266006 TCPC p0 Low Power Mode] [7059.225553 power state 9 = S5->G3, in 0x000c] [7059.226188 chipset_force_shutdown()] [7059.226717 PB PCH force press] [7059.233871 PB PCH pwrbtn=LOW] [7059.234381 power state 0 = G3, in 0x000c] [7059.250255 power state 0 = G3, in 0x000f] [7059.256533 SW 0x05] Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://chromium-review.googlesource.com/683956 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* stoney: Remove throttle cpu from S3S0 power stateAkshu Agrawal2017-05-201-6/+0
| | | | | | | | | | | | | | This was causing cpu to give lower performance. Hard throttling is being handled in chipset_throttle_cpu. BUG=None TEST=Improved CPU benchmark Change-Id: I0bff47ec0ce60f31fa1f30fdea94d45dfe05aa38 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://chromium-review.googlesource.com/508569 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* kahlee: initial board settingJimmy Wang2017-04-051-0/+267
1. GPIO initial 2. board config 3. led control 4. power control of Stoney 5. battery setting BRANCH=None BUG=None TEST=power on device and test manually Change-Id: I14cc60bf2cdd40032b3cbdfacf68d7a3c17fe87c Reviewed-on: https://chromium-review.googlesource.com/461624 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Lin Cloud <cloud_lin@compal.com> Tested-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>