| Commit message (Collapse) | Author | Age | Files | Lines |
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Reconfigure the SLP_S3_L power interrupt as an output and drive this
signal low while the PP3300_A rail comes up. This prevents a glitch on
the SLP_S3_L signal that can affect the power sequencing.
BUG=b:143346794
BRANCH=none
TEST=make buildall
TEST=Verify Volteer boots. With debug code enabled, verify SLP_S3_L
drives low while PP3300 turns on.
Change-Id: Ic8204874cb9e68a1af27fafcf5274d50ce5cb38f
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068535
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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"enum ec_current_image" is exposed in ec_commands.h (and used by non-EC
code, such as biod).
We also have an "enum system_image_copy_t" that is the exact same thing
(though has a few more definitions).
A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the
"sysinfo" host command, so we want to be able to expose all the
potential image variants. Rather than maintain two enums that can
potentially get out of sync, unify the code to use a single enum. We
choose to keep the "enum ec_current_image", since external code depends
on it.
To verify that this change results in no changes to the generated
binaries:
./util/compare_build.sh --board all
BRANCH=none
BUG=b:146447208
TEST=./util/compare_build.sh --board=all
Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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Some boards need different mechanisms to enable/disable the 5V rail
that's not simply setting the PP5000_EN GPIO. This commit adds a new
board specific API to control the 5V rail. If a board needs something
more complex, they should define `board_power_5v_enable`.
BUG=b:149794574
BRANCH=None
TEST=Add definition for waddledoo, build and flash, verify that
sub-board 5V is turn on as well.
Change-Id: I333e3fb8f2b4e7f1907c792c0e35581150857f17
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065494
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Some x86 boards need to perform some workarounds after handling
RSMRST_L, therefore this commit adds a CONFIG_* option to enable this,
CONFIG_BOARD_HAS_AFTER_RSMRST. A board callback, board_after_rsmrst()
will be called after RSMRST is changed.
BUG=b:148688874
BRANCH=None
TEST=Enable CONFIG_* option, verify that callback is called once RSMRST
changes.
Change-Id: Ic6b6b4a0f23639e3fd4d9e69c95b3d94e44a2162
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2058693
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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In some boot cycles, identified a case where PG_DRAM_OD
not getting SET when EC already transitioned to S0.
PG_DRAM_OD taking around 5+ms to get SET, after SLP_S3_L SET.
In such cases, intel_x86_get_pg_ec_all_sys_pwrgd() returns 0
and PCH_SYS_PWROK remaining as 0.
BUG=b:147257114
BRANCH=None
TEST=make -j BOARD=waddledoo; flash waddledoo, verify that
DUT can boot to S0.
Change-Id: I09207c723d3d006e8a555c3c2d44aa6ed5cc027d
Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054363
Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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As per Waddledoo power sequencing requirements,
1. ALL_SYS_PWRGD should be driven based on DRAM power good and
the PP1050_ST power good.
2. the EC needs to assert EC_AP_PCH_PWROK_OD, with a 2ms minimum
delay after receiving the DRAM power good and the PP1050_ST power good.
3. Enable CONFIG_BACKLIGHT_LID
BUG=b:147257114
BRANCH=None
TEST=make -j BOARD=waddledoo; flash waddledoo, verify that
DUT can boot to S0.
Change-Id: I5ad226faa15cfe8ae569524decf405bbd378a28c
Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044250
Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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When sysjump to RW, the sleep mask is cleared. Should mask the AP_RUN
bit to prevent deep sleep.
BRANCH=None
BUG=b:149337916
TEST=Reboot EC/AP, sysjump to rw; checked dsleep AP_RUN bit set.
Change-Id: I7b11132eb464bf6d28432884b90ba292e7f56847
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057971
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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With the adapter to activate the smart battery which is shutdown
mode, will enable PMIC during activation and have heavy loading,
which will prevent the system from powering on. Delay to boot
system until the smart battry is ready.
BUG=b:148045048
TEST=1) When battery is cutoff mode or shutdown mode, DUT will
4 second to boot, which activated with the adapter.
And the return value of system_get_reset_flags() is 0x02.
2) Power off the DUT with click the UI icon 'Shut down' or
long press the power button. And the return value of
system_get_reset_flags() is 0x802.
Both test 1 and 2 can boot DUT.
BRANCH=kukui
Change-Id: Icb4ed75dbca13fef4c44e5386b7b957a12970557
Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2049929
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring
the benefts to Chromebooks, which are:
- Reduce RO dependency and presence. Allow more code to be updated
in the fields.
- Remove jumptag and workarounds needed for late sysjump.
Major imporvements over v1 are:
- No A/B slot required.
- No signature in RW or public key in RO.
- Rollback-attack protection.
- Verifies only RW being used instead of whole RW section.
For battery-equipped devices, additional benefts are:
- Immediate boot on drained battery.
- Support recovery mode regardless of battery condition.
- Faster charge in S5/G3.
EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm).
EFS2 is documented in go/ec-efs2.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chromium:1045217,chromium:141143112
BRANCH=none
TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode.
TEST=Wake up EC from hibernate.
TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep.
Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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System will trigger reset when already force to G3.
Add board_chipset_forced_shutdown() in chipset_force_shutdown to
stop reset when system force to G3.
BUG=b:143440730
BRANCH=master
TEST=Power on system and make system enter G3 immediately.
Make sure system won't reset.
Change-Id: Ie601921af9adf08d2055cdecb0243e64bd57724f
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014001
Tested-by: David Huang <david.huang@quanta.corp-partner.google.com>
Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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TEST=Verified proto can turn off the relevant core rails:
* Pretend to be an EVT board: ectool cbi set 0 1
* Reboot EC
* Drop to S0ix: echo freeze > /sys/power/state
* Verify CPU_C10_GATE is asserted (powerindebug) and EN_S0_RAILS
is deasserted (gpioget EN_S0_RAILS)
* Wake system and ensure it resumes correctly
BUG=b:144719399
BRANCH=None
Change-Id: I8e4158ffac38461e8679ac49a084b4296bcef210
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035432
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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For Jasperlake, the EC needs to assert EC_AP_VCCST power good with a 2ms
minimum delay after receiving the DRAM power good and the PP1050_ST
power good.
BUG=b:148688874
BRANCH=None
TEST=`make -j buildall`
Change-Id: Ieedabf5a8a7af3951910118504dc702f7f8058bc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036453
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Per the power sequencing requirements, VCCIO_EXT, new for JSL, should be
driven based off of SLP_S3_L deassertion/assertion.
BUG=b:148630993
BRANCH=None
TEST=Build and flash waddledoo, boot to S0, verify that VCCIO_EXT is
enabled. Shutdown, verify it's disabled.
Change-Id: I2a25b29ebbde94eabf6b71c5c02252ebbd6ad1d9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032728
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This commit makes power_signal_get_level() overridable as there are some
boards (like dedede) which have power sequencing inputs which are not
simply just GPIOs nor eSPI VW.
BUG=b:148169171
BRANCH=None
TEST=`make -j buildall`
Change-Id: I16fbf54b0688b432c82312a431f1d9f7cc074278
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032727
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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The original one interrupt handler for two signals will cause a
false-postive for the WARM_RESET_L release case, during a transition
state that POWER_GOOD goes low but WARM_RESET_L is still high.
Use two interrupt handlers for WARM_RESET_L and its pull-up rail
POWER_GOOD. It is clear that what signal triggers the interrupt.
BRANCH=None
BUG=b:148478178
TEST=Called "dut-control warm_reset:on sleep:0.2 warm_reset:off" and
saw the message "Long warm reset ended, cold resetting to restore
sanity" once.
Change-Id: I5a14f91c0dbfacd6a70d01d45f3e8de2b6c6a1cc
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031647
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Tested-by: Alexandru M Stan <amstan@chromium.org>
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For two of the complicated cases in the power sequence, the ec is being very
chatty but it's hard to understand why it's doing certain things (or if there
was an exception). Add more prints to be clearer.
BRANCH=None
TEST=releasing warm reset via servo should have an extra print on
why it's going to S5 and back to S0
TEST="apreset" with bad AP firmware will cause EC to complain
BUG=b/148188311
Change-Id: I2d53dfc553639ecec0792d78676b0899e3e76780
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023404
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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This trigger is not necessary for production use case. Remove it.
BRANCH=None
BUG=b:147818450
TEST=sysjump to RW, checked that AP keeps the same state.
TEST=Tested reboot ap-off, checked that AP off from reset.
TEST=Tested commands: apreset, power off, power on, apshutdown.
Change-Id: Ia7ebd9d56ed70ec902224bff7d6308bc37e7fa1e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018040
Commit-Queue: Alexandru M Stan <amstan@chromium.org>
Tested-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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This logic is no longer used. Should be deprecated.
BRANCH=None
BUG=b:148238496
TEST=Assert the AP_RST_REQ signal, no reboot happens.
Change-Id: Icade7ede9a8fb48313123ad59b5a36a8aa1a71bf
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018056
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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When checking the event for power on or power off, should check the
power_request first such that this request can be cleared; otherwise,
the request still presents and may result a loop.
BRANCH=None
BUG=b:145901185
TEST=Toggle the WARM_RESET_L signal and no loop happens.
Change-Id: Ifb79107d40b9a4c8e71a459ccd3063a0cacede17
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1963378
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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This appears to be an artifact left over from skylake (where the EC
can't turn off the AP without also turning itself off) that was copied
into cometlake and from there into cometlake-discrete. Since we never
mess with the power button like skylake does, there's no reason to
include that handling.
TEST=no effect on puff's behavior
BUG=None
BRANCH=None
Change-Id: Id383e5b7b28e7cca7c5f5e1fb0d8840a1c15bffa
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014002
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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Without this, apshutdown on the EC console turns off the system but it
thinks it's in S5 when it's actually in G3 so it doesn't respond to
power button presses to turn back on. Make the steady-state S5 handling
check whether the system is actually in S5 and transition down as
appropriate.
TEST=puff goes directly to G3 on apshutdown, but not when shutting down
gracefully.
BUG=b:147461413
BRANCH=None
Change-Id: Ic216b5e908b8a77d8d016f60dd8b0de832cf301e
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014000
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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The common Intel code looks at IN_PGOOD_ALL_CORE in steady-state S3 and
S0, forcing a shutdown if any part of it goes away. By including the
DRAM rails, we make it think there's a power failure during orderly
shutdown because the PCH turns off the things it controls before the EC
notices it's transitioning (they're not in lockstep, the PCH goes as
fast as it wants and the EC must catch up).
This means the only time we can actually monitor the DRAM rails is when
bringing them up, since the PCH may turn them off.
BUG=b:147461413
TEST=puff now responds to power button press in S5 after shutdown, and
does not log power failure.
BRANCH=None
Change-Id: Ia18c06ea2eec54c4ff0ccad3c91ba29547014f9c
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009541
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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Monitor GPIO PG_EC_ALL_SYS_PWRG was not trigger,
when power on within 3 seond, EC will reset system.
BUG=b:143440730
BRANCH=master
TEST=check boot to OS was workable
Change-Id: I19f2411a5369c75b6895316b791d077e2aee7deb
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948690
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com>
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Jasperlake uses the same chipset driver as Icelake and the dedede
reference design does not have a distinct pins for a couple of the power
good signals. In order to accommodate this, this CL allows some of the
power good signals to be overidden by a board specific implementation.
These power good signals are PG_EC_DSW_PWROK and PG_ALL_SYS_PWRGD.
BUG=b:147257114
BRANCH=None
TEST=`make -j buildall`
Change-Id: I3d889ed9d17bf224a69d1de188fe15933140d606
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1987836
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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Configs mostly copied from fizz.
TEST=booted on hardware, observed successful jump to RW.
BRANCH=none
BUG=b:146504182
Change-Id: Icf2925b92fea848efcd705bb5274d1afc91d2513
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1977079
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Commit-Queue: Andrew McRae <amcrae@chromium.org>
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The common x86 state machine does this, but the EC-controlled sequencing
did not. Since trying to boot the AP without enough power will cause
the system to brown out, we need to do it too.
TEST=boot prevented on hardware
BRANCH=none
BUG=b:146515963
Change-Id: I7dbe6ab962fbe47d4d866be98d4174291c757c72
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980104
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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- Jasperlake power sequencing flow is same as Icelake
- Rename CONFIG_CHIPSET_ICL_TGL as CONFIG_CHIPSET_ICELAKE
to avoid duplicate code
- define CONFIG_CHIPSET_ICELAKE on CONFIG_CHIPSET_JASPERLAKE or
CONFIG_CHIPSET_TIGERLAKE
BRANCH=none
BUG=b:146693933
TEST=make buildall -j
Change-Id: I25f43d85fcfc7fbbfe06787e5a201983c0e49cc7
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980090
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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The VBOB rail is for backup only. Verified the hardware that it works
without this rail. Should be OK to remove the control of it.
BRANCH=None
BUG=b:143616352
TEST=Verified AP power on and power off.
Change-Id: I9632d881b590482a07482e23aba88bc7ffec4521
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955108
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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The original check in the init hook (power_chipset_init) may cause
watchdog reset, as the init hook is earlier than the task execution
that we should not perform any long action, like waiting for a signal
in our case.
We should simply turn off the switchcap without any check.
In most of the common cases (except flashing EC/AP), the switchcap
should be off and the check is unnecessary.
BRANCH=None
BUG=b:145843686
TEST=Performed flashing EC and AP, EC watchdog reset not seen.
Change-Id: I36873e773800def7e3dfceaec28c294dee9a09c7
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955107
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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The new ectool command 'ectool reboot_ap_on_g3' will reboot AP from
G3 state on initiation of DUT shutdown. Thus eliminating the dependency
of servo to trigger wake events when testing AP cold boot cycles.
BUG=b:129507479
BRANCH=None
TEST=Tested on hatch board.
From Kernel console, entered the below commands:
$ectool reboot_ap_on_g3
$shutdown -h now
Observed AP boots back to S0 upon G3.
Change-Id: Ie6fcbd2f00eb6c22ed498ab82dac53132dbbf4a3
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918993
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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The power rail should be turned on at G3S5 rather than S5S3,
and should be turned off after stay in G3 for 20ms.
TEST=Ensure the power rail is on/off at correct timing
BUG=b:144144075 b:145255107
BRANCH=none
Change-Id: Ie621ab1ac5332da6718201c44266f41aafcac296
Signed-off-by: Yilun Lin <yllin@chromium.org>
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928413
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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A first go at the power sequencing needed for Puff. This abuses the
Intel common power code a little bit because we don't actually have all
the inputs it assumes, but that seems preferable to replacing it
wholesale.
The one limitation right now is inability to detect transitions on the
rails that we only have analog monitoring on; either we need to design
a way to monitor those, or decide that detecting dropouts on those rails
is unimportant.
BUG=b:143188569
TEST=still builds
BRANCH=None
Change-Id: Ia960f5dd2ccfb1ca2c7d4107ba4e3737adc8f69f
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925787
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This is an initial commit for Trogdor. Use Cheza as a baseline.
Make the change according to the schematic, e.g.
* Reflect the GPIO change
* Reflect the TCPC/PPC part change
* Update the USB topology, e.g. no device mode support
* Remove the detachable related code
* Add keyboard support
* Support keyboard backlight
* Update the battery characteristic
* Add initial support of muxing DP path
* Support a single USB-A port
* Change sensors from lid to base
* Minor code style improvement
BRANCH=None
BUG=b:143616352
TEST=BOARD=trogdor make
Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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This sets up the driver (mostly copied from cometlake for now), to be
used by puff.
BUG=b:143188569
TEST=make buildall still succeeds
BRANCH=none
Change-Id: I4a4b70dd8ba58c070e2c6ad5941911bab16bafe6
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906391
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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On Volteer, to avoid leakage from PP3300_A rail to PP5000 rail, turn on
the PP3300 rail before PP5000.
BUG=none
BRANCH=none
TEST=make buildall -j
TEST=verify Volteer transitions to S0
Change-Id: Ic86f97dbdde6d6c904fe7efc8b0edc1ead727cf6
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918603
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Add additional debug output for Ice Lake and Tiger Lake power sequencing
when the CONFIG_BRINGUP option is enabled.
BUG=none
BRANCH=none
TEST=make buildall
TEST=Verify debug messages on Volteer when CONFIG_BRINGUP is enabled.
Change-Id: I80fc23f470818af7a4dad73a7ad77bc9ba42d537
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918602
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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To prevent mispressed cases, we decide to increase
the power button press boot time to at least 1s.
TEST=aps; powerbtn $sec; where $sec is between 0~1000 and see it
won't boot
TEST=aps; powerbtn $sec; where $sec > 1000 and see it boot
TEST=aps; ensures the physical power button press is working as
expected.
BUG=b:131856041
BRANCH=kukui
Change-Id: Ie3099ba9639a729cee77b7d444a459fbef72733d
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906387
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the
PCH signal PCH_SYS_PWROK.
These signals correspond to the Intel signal names ALL_SYS_PWRGD and
PCH_SYS_PWROK, respectively.
BUG=b:143373337
BRANCH=none
TEST=make buildall -j
Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753
Commit-Queue: Sean Abraham <seanabraham@chromium.org>
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Add X86 prefix to the Comet Lake signals names for consistency with
other Intel APs.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into
separate options controlling SLP_S3 and SLP_S4. Allow volteer to
configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a
build error if virtual wires are configured, but eSPI is not.
BUG=b:139553375,b:143288478
TEST=make buildall
TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but
CONFIG_HOSTCMD_ESPI undefined; observe build error
BRANCH=none
Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758
Reviewed-by: Keith Short <keithshort@chromium.org>
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Change GPIO_EC_PCH_DSW_PWROK to GPIO_PCH_DSW_PWROK to match convention
for EC to PCH signals used by other Intel processors (specifically
cannonlake already used GPIO_PCH_DSW_PWROK).
BUG=none
BRANCH=none
TEST=buildall -j
Change-Id: I59fb8d3ee3867c70dde74c186ba3974490c3cd27
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848252
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Change GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK on cometlake to
conform with naming convention used on other Intel processors.
Leave gpio.inc files unchanged and add a mapping from
GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK in the board files.
BUG=none
BRANCH=none
TEST=make buildall -j
TEST=boot kohaku
Change-Id: I722cb06dd90ee5d7e426664508f54a5cbe19de4a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848251
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Replaced references of GPIO_EC_PCH_RSMRST_L with GPIO_PCH_RSMRST_L in
to match convention used in common Intel power sequencing. Boards
still use GPIO_EC_PCH_RSMRST_L in their gpio.inc files to match
schematic net names.
BUG=none
BRANCH=none
TEST=buildall -j
TEST=boot kohaku (cometlake device)
TEST=run "apshutdown" on kohaku
Change-Id: Ic9fa13dbf2d4e6c8953b82a9dd20f48a6cf8d2c8
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846690
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Regardless of the state of CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS, if
CONFIG_HOSTCMD_ESPI is enabled, then the AP can still generate virtual
wire interrupts.
Replace checks of CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS for power signals
with CONFIG_HOSTCMD_ESPI.
This fixes a processor exception that was caused by siglog_add() when
the AP generated a virtual wire interrupt. The VW signals start at
GPIO_COUNT so were causing buffer overflows of gpio_list[].
BUG=b:142406787
BRANCH=none
TEST=buildall -j
TEST=Enable CONFIG_BRINGUP on kohaku. Without change RO causes
processor exception, with change RO and RW boots and AP boots.
Change-Id: I81ab6f2fed217f5aad3ca7fae64c850e3af49f43
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1850275
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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To improve G3 power consumption, a pin EN_PP1800_S5_L is added in board
rev 1 and should be turned on before pmic on, and turned off after pmic
off.
BUG=b:138180455,b:141592177
TEST=verify jacuzzi rev 1 is bootable with this change
BRANCH=master
Change-Id: Iacd9b0fab97d775f15faa9b2df491940871bc7ff
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1773031
Reviewed-by: Yilun Lin <yllin@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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This change fixes the printf formatting errors found by the
compile-time prinf format checker. The errors fall into a few
categories:
1. Incorrect size specifier (missing or extra l).
2. Missing or extra arguments.
3. Bad line splitting.
BUG=chromium:984041
TEST=make -j buildall
BRANCH=none
Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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In order to make our printf more standard, utilize %ll for long long
arguments, rather than %l. This does cost a little bit in flash space
for that extra l in a couple of places, but enables us to turn on
compile-time printf format checking.
For this commit only, the semantics are such that both %l and %ll
take 64-bit arguments. In the next commit, %l goes to its correct
behavior of taking a sizeof(long) argument.
BUG=chromium:984041
TEST=make -j buildall
BRANCH=none
Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029
Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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If the host command handler callback function returns an int, it's easy
to accidentally mix up the enum ec_error_list and enum ec_status types.
The host commands always expect an enum ec_status type, so we change the
return value to be of that explicit type. Compilation will then fail if
you accidentally try to return an enum ec_error_list value.
Ran the following commands and then manually fixed up a few remaining
instances that were not caught:
git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\
xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\
static enum ec_status \1(struct host_cmd_handler_args \*args)##'
git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\
xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\
enum ec_status \1(struct host_cmd_handler_args \*args)##'
BRANCH=none
BUG=chromium:1004831
TEST=make buildall -j
Cq-Depend: chrome-internal:1872675
Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Add support for the RTC reset on Volteer. This change also deduplicates
the board_rtc_reset() function which was identical on boards that
enabled CONFIG_BOARD_HAS_RTC_RESET.
BUG=b:141321096
BRANCH=none
TEST=make buildall
Change-Id: Ifc6959f8271400174fd4999a3c70800b03b9c2d0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816869
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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There was a todo to replace a while loop with a call to
power_wait_signals_timeout. However, using that function is not
feasible in this case as it's only intended to check for power signals
that are high. Removing the TODO comment since it's not applicable.
BUG=b:122264541
BRANCH=None
TEST=make BOARD=hatch
Change-Id: I0dca060f8a8e00bc99a433d78dd55d262a867cb1
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1783521
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
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