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* power/rk3399: Change power-off sequence for KD panelPhilip Chen2018-01-161-1/+1
| | | | | | | | | | | | | | | | | We should turn off PP3300_S0 and then PP1800_S0 to meet KD panel spec. PP3300_S0 has to be on in S3_WoUSB, so PP1800_S0 also has to be on - let's move PP1800_S0_EN to s0s3_usb_wake_power_seq. BUG=b:71057948 BRANCH=none TEST='suspend_stress_test' for 10+ cycles without seeing things go wrong Change-Id: Ic44411062b4c9e857b9f8ca6565550ba8bd2f950 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/862254 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMIShamile Khan2018-01-161-0/+4
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=GLKRVP can boot to OS when a coreboot image with eSPI enabled is flashed. Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/818196 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* grunt: Fix ENABLE_BACKLIGHT to be active lowEdward Hill2018-01-141-4/+0
| | | | | | | | | | | | | | BUG=b:71806495 BRANCH=none TEST=backlight turns on in S0 Change-Id: Ib9271d6cbe9befdf4ed492a9c2b676452e5f4d9b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865155 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power: Fix interrupt enable in siglog_deferredEdward Hill2018-01-111-1/+1
| | | | | | | | | | | | | | | | Recent eSPI change (d813935) resulted in siglog_deferred leaving interrupts disabled. BUG=b:71764538 BRANCH=none TEST=apshutdown on grunt, see power signal changes Change-Id: I33e234ad7191af92e2c4ffef700fc5b9356c3c71 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/860571 Commit-Ready: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
* espi: Add API to test if signal is eSPI virtual wireScott Worley2018-01-022-12/+20
| | | | | | | | | | | | | | | | | | | | | | Add espi_signal_is_vw in new file common/espi.c for testing if a signal is an eSPI virtual wire. API used in power common and intel_x86. Fix CONFIG_BRINGUP support for eSPI (off by default). Add espi_vw_get_wire_name returning a pointer to constant string. Chip modules do not need to maintain names of eSPI signals. BRANCH=none BUG= TEST=Build poppy and other eSPI enabled boards. Test power state machine. Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/836818 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Fix the power sequence length passed to power_seq_run()Philip Chen2017-12-201-2/+2
| | | | | | | | | BUG=b:63037490 BRANCH=none TEST=build scarlet Change-Id: I80b068a7846037f43e7b385cf8e2ee0b08f42b15 Signed-off-by: Philip Chen <philipchen@google.com>
* cleanup: power/rk3399: Remove unused power sequencePhilip Chen2017-12-201-45/+0
| | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I87c7a6274cbcb355a71987b26e8f092fbdbe8fa0 Signed-off-by: Philip Chen <philipchen@google.com>
* power: cannonlake: SLP_SUS_L deasserted == S5.Aseda Aboagye2017-12-201-0/+6
| | | | | | | | | | | | | | | | When SLP_SUS_L is deasserted, that means the chipset is in S5. BUG=None BRANCH=None TEST=Flash meowth; boot from AC only, verify that when SoC actually boots the power state is reported as S0 instead of G3. Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/837485 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: cannonlake: Fix power state tracking.Aseda Aboagye2017-12-121-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cannonlake power state chipset code would fail to keep an accurate record of the chipset's power state. For example, the EC could claim that the AP was in G3, whereas the SLP_SUS_L signal was deasserted. This commit fixes a few issues with the chipset code. - First, don't have PP3300_DSW_EN enabled by default coming out of reset. The default chipset power state when the EC comes out of reset is G3, therefore we should not enable the PP33000 DSW rail until we decide to leave G3. This is usually triggered by a power button press. - Similarly, when we wish to enter G3, we should turn off the PP3300 DSW rail instead of the noop that was done before. - Lastly, turn on the 5V rail when entering S5 instead of S3 and turn it off when leaving S5 to G3. BUG=b:70184397,b:70244199 BRANCH=None TEST=Flash zoombini; Verify that AP boots to S0 and can shutdown to S5 and the EC tracks it. Verify that after the S5 inactivity timer, we fall to G3. Verify that SLP_SUS_L is asserted and DSWPWROK is low. Verify that we can still perform BC1.2 detection in G3. `reboot ap-off` and verify that the AP does indeed remain off and no port 80 codes are seen. TEST=Verify that 5V is off in G3, but can be turned on if needed. TEST=Verify that 5V is on in S5. TEST=With the exception of BC1.2, repeat the above tests for meowth. Change-Id: I444a8f29969ef6a68a83d1734912d239bad429a5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/813501 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/rk3399: Poll IN_PGOOD_S0 on up-sequenceShawn Nematbakhsh2017-12-121-4/+23
| | | | | | | | | | | | | | | | | | | | | | Waiting out HOOK_TICK_INTERVAL for a non-interrupt power signal can cause boot delays of up to 500ms, which can lead to dropped host commands and other bad side effects. Poll IN_PGOOD_S0 when sequencing up to reduce the minimum delay to 5ms. BUG=b:70390178 BRANCH=None TEST=Run "reboot" on EC console, check timestamp of S0 transition print: [0.332974 power state 3 = S0, in 0x000f] Compare to pre-patch: [0.692799 power state 3 = S0, in 0x000f] Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4b8891f75d896b1ae47d8f12ed07581f20b6ae7c Reviewed-on: https://chromium-review.googlesource.com/822594 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* grunt: Add delay to PWR_GOODEdward Hill2017-12-112-20/+9
| | | | | | | | | | | | | | | | | | Add delay of 1ms with stable power before asserting PWR_GOOD. CDX03 seems to work ok with and without the delay, but since it is a requirement in the electrical data sheet, better add it. Also removed an unnecessary header while I was here. BUG=b:70350333 BRANCH=none TEST=power CDX03 on and off Change-Id: I9f2f94bfb907ac9e88f350e72286061a97ebfe3d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/816063 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* host_events: Introduce unified host event commandJenny TC2017-12-062-49/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=make buildall -j. And verfieid following scenario 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC(making get_feature_flags1() return 0) Change-Id: Idb82ee87fffb475cd3fa9771bf7a5efda67af616 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/576047 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Commit-Ready: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Auto power-on after battery SOC is above minimum requiredFurquan Shaikh2017-11-281-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | If power-up is inhibited by charger because of battery SOC, then check for the conditions again on BATTERY_SOC_CHANGE. This allows the EC to boot the AP up on connecting AC power and SOC going above the minimum required. BUG=b:65864825 BRANCH=None TEST=Verified following on coral and soraka: 1. Discharge battery to ~0% 2. Connect AC power ==> Power-up is inhibited 3. When battery SOC reaches 1%. AP is not taken out of reset: "[12.974428 Battery 1% / 8h:4 to full] [12.980439 power-up still inhibited]" 4. When battery SOC reaches 2%, AP is taken out of reset: "[9.230148 Battery 2% / 4h:5 to full] [9.236122 Battery SOC ok to boot AP!]" Change-Id: Ifa89f8929987d86c9e02530b663d563dbe25ed85 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753294 Reviewed-by: Shawn N <shawnn@chromium.org>
* cannonlake: Check for hard and soft off in chipset_force_shutdownFurquan Shaikh2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | Similar to CL:774298, intention of chipset_force_shutdown is to power off the AP by simulating power button press until it results in power button override and shuts down AP. However, if AP is already in hard or soft off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already off, and simulating power button press results in charge_prevent_power_on from incorrectly assuming that the power button is pressed by user. Thus, check if the system is in soft or hard off before shutting it down. BUG=b:65864825 BRANCH=None TEST=make -j buildall Change-Id: I4b6d798af4618cbd4179f8700ebb2aa78021207e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/791933 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: Check for hard and soft off in chipset_force_shutdownFurquan Shaikh2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | Intention of chipset_force_shutdown is to power off the AP by simulating power button press until it results in power button override and shuts down AP. However, if AP is already in hard or soft off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already off, and simulating power button press results in charge_prevent_power_on from incorrectly assuming that the power button is pressed by user. Thus, check if the system is in soft or hard off before shutting it down. BUG=b:65864825 BRANCH=None TEST=Verified that apshutdown still works fine from EC console on soraka. Change-Id: Id892e5b2c8c1e4ce0bad95a70ea6a3ed547a7047 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/774298 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Meowth: Added initial board file.Rachel Nancollas2017-11-151-1/+1
| | | | | | | | | | | | | | | | | | | Created Meowth symbolic link to Zoombini. Modified Zoombini gpio.inc and board, etc. files to compile a Meowth EC image with the correct gpios. BUG=b:69133424 BRANCH=none TEST=make BOARD=meowth and BOARD=zoombini runs with no errors Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122 Signed-off-by: Rachel Nancollas <rachelsn@google.com> Reviewed-on: https://chromium-review.googlesource.com/762039 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Revert "power: Get rid of power_board_handle_host_sleep_event"Furquan Shaikh2017-11-151-1/+11
| | | | | | | | | | | | | | | | | This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271. This is required to ensure that PMIC VR decay is enabled before SLP_S0# is asserted. Else, the setting does not take effect and hence results in higher power consumption. BUG=b:69337192 BRANCH=None TEST=make -j buildall Change-Id: I6885e7447277d853a2414be299dfea25f5547df4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771054 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* kahlee: Don't hold pwrbtn=LOW in G3Edward Hill2017-11-031-1/+1
| | | | | | | | | | | | | | | Change chipset_force_shutdown() to not call power_button_pch_press() when called from POWER_S5G3 state, so that we don't set pwrbtn=LOW when entering G3. BUG=b:68760602 BRANCH=none TEST=push kahlee power button Change-Id: I931fc73f2386f8124f1e082cccb095e3863cbb99 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/752682 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Get rid of power_board_handle_host_sleep_eventFurquan Shaikh2017-10-311-11/+1
| | | | | | | | | | | | | | | | | power_board_handle_host_sleep_event was added to allow boards like poppy to enable/disable PMIC VR decay only once during S0ix entry/exit. Now that the chipset hooks have been fixed, there is no need of this board specific callback. If in the future, there is a need to have such a callback, this change can be reverted. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745982 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Add default sleep event state HOST_SLEEP_EVENT_DEFAULT_RESETFurquan Shaikh2017-10-312-5/+7
| | | | | | | | | | | | | | | | | | Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to reinitialize S0ix flag, add a new default state HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of the code to take correct action depending upon the state that is currently triggered. BUG=None BRANCH=None TEST=Verified that SLP_S0# interrupt doesn't get asserted during runtime S0ix. Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745901 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* zoombini: cannonlake: Add 5V power good signal.Aseda Aboagye2017-10-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The 5V power good signal is being removed from the PMIC power good tree, however, if the 5V power good is not asserted, we should not try booting to S0. This is because the 1050_STG rail load switch is powered off of the 5V rail. Since wireless power control is being moved to the AP, these pins are now repurposed to control the PMIC enable and for the 5V power good signal. This commit adds the 5V power good pin to the EC and makes it a required power signal for S0. BUG=b:66000679 BRANCH=None TEST=make -j buildall TEST=flash zoombini; Verify EC boots up okay. Change-Id: I8924320030a00b8808aea27fb668451e6e41d590 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/736312 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/intel_x86: Fix S0ix suspend/resume hook notificationsFurquan Shaikh2017-10-241-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a fundamental difference in host behavior w.r.t. S3 and S0ix. When the host enters S3, it asserts the SLP_S3# signal until it is woken back up. Thus, EC depends on the SLP_S3# signal state to decide when to notify listeners about CHIPSET_SUSPEND and CHIPSET_RESUME state. With S0ix, SLP_S0# signal is asserted whenever host enters S0ix. However, periodically (every 8 seconds), the host wakes up for some bookkeeping activities, but does not come out of the low power mode completely. This bookkeeping activity takes ~2-5 ms and the host goes back into S0ix state. Because of this periodic activity, SLP_S0# signal is de-asserted and asserted back every 8 seconds. Thus, if the power state machine depends solely on the SLP_S0# signal to notify CHIPSET_SUSPEND and CHIPSET_RESUME states, then all the listeners would be performing unnecessary actions every 8 seconds. This leads to a number of side-effects including: 1. Dual-role toggle being enabled and disabled every 8 seconds. 2. Power spikes in EC power consumption during S0ix every 8 seconds. In order to avoid the side-effects of periodic host activity in S0ix, this change adds a new flag s0ix_notify, which is set based on the notifications that are pending based on host sleep event. On receiving host sleep event for S0ix suspend, s0ix_notify will be set to S0IX_NOTIFY_SUSPEND. Next, whenever SLP_S0# is asserted, power_state machine notifies listeners of CHIPSET_SUSPEND and resets s0ix_notify flag to S0IX_NOTIFY_NONE. Thus, all future assertions of SLP_S0# do not result in the suspend notification. Similarly, on resume, power_state machine will not notify CHIPSET_RESUME on SLP_S0# deassertion. Instead the host sleep event for S0ix resume will set s0ix_notify flag to S0IX_NOTIFY_RESUME and wake chipset task. The power state machine in turn will notify listeners of the resume event and reset s0ix_notify flag. BUG=b:65356050,b:67750352 BRANCH=None TEST=Verified that the CHIPSET_SUSPEND/CHIPSET_RESUME notification happens only once during a system suspend/resume cycle. Periodic host wakes for book-keeping activities do not result in CHIPSET_SUSPEND/CHIPSET_RESUME notifications. Change-Id: Idf253b9393a0c25ff2eac63c60ddbcd3af954818 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/729478 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Add task-safe API to control 5V rail.Aseda Aboagye2017-10-232-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For certain cannonlake designs, the 5V rail can be controlled by both the chipset task as well as other tasks such as the USB charger tasks to perform BC1.2 detection. This commit introduces an API that allows the tasks to enable/disable the 5V rail. Enable requests will immediately enable the rail, however, attempting to disable the rail will only result in a request. Once all tasks want to turn off the 5V rail, the rail will be turned off. A bitmask is introduced to keep track of the requests. Index 0 is for the chipset task. All of this is gated behind a config option: CONFIG_POWER_PP5000_CONTROL BUG=b:65991615 BRANCH=None TEST=With other zoombini code, verify that 5V can be enabled and disabled. Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/722322 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/intel_x86: Give host a chance to read hostevents on S0ix wakeFurquan Shaikh2017-10-191-6/+5
| | | | | | | | | | | | | | | | | Instead of clearing out all the host events on S0ix wake, provide an opportunity to the host to read the events and log it. Move the call to clear events to the point where host sends a command indicating exit from S0ix. BUG=b:67874513 BRANCH=None TEST=make -j buildall. Verified that host events are cleared by the host during logging. Change-Id: I339dc70d761bb851286d98c5c20094ccaefd238f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/724188 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exitFurquan Shaikh2017-10-031-0/+7
| | | | | | | | | | | | | | | | | | | Runtime S0ix results in SLP_S0 signal being toggled continuously resulting in an interrupt storm on the EC. In order to avoid this, enable SLP_S0 power signal only when host indicates intent to enter S0ix and disable when host exits from S0ix. BUG=b:65421825 BRANCH=None TEST=Verified that runtime S0ix no longer results in interrupt storm on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0 using powerindebug. Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Call power_chipset_handle_host_sleep_event on state resetFurquan Shaikh2017-10-031-0/+1
| | | | | | | | | | | | | | | | Any time the host sleep state is updated (including reset of host sleep state), make a callback into power_chipset_handle_host_sleep_event to allow mainboard and chipset to take any necessary action. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: Ib4d35fa0b417500090361e4e26415feedb663e35 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/683797 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Add flag to disable power signal at bootFurquan Shaikh2017-10-031-1/+4
| | | | | | | | | | | | | | | Add a new flag to allow boards to indicate if a power signal has to be enabled/disabled at boot. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: Ibe7ab74e8191c58433087d8024b344d7e845f17e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679981 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power: Expose power_signal_{enable/disable}_interrupt outside power/common.cFurquan Shaikh2017-10-031-1/+11
| | | | | | | | | | | | | | | 1. Make power_signal_enable_interrupt visible outside power/common.c 2. Add corresponding power_signal_disable_interrupt function. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: I04b7b053cc1ffe978fcbac5b2cb746d21b198aa2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679980 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power: Add flags parameter to power_signal_infoFurquan Shaikh2017-10-032-2/+8
| | | | | | | | | | | | | | | | | | | | | | Replace structure member "level" in power_signal_info with "flags". "level" has been used on all boards to indicate active-high or active-low levels. Addition of "flags" allows easy extension of power_signal_info structure to define various flags that might be applicable to power signals (e.g. "level"). Going forward, additional flag will be added in follow-up CLs. Also, provide a helper function power_signal_is_asserted that checks the actual level of a signal and compares it to the flags level to identify if a power signal is asserted. BUG=b:65421825 BRANCH=None TEST=make -j buildall Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/679979 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Fizz: Initialize PMIC after AP power is readyDaisuke Nojiri2017-09-291-11/+9
| | | | | | | | | | | | | | | | | On proto3, PMIC isn't powered on POR, thus board_pmic_init fails. With this change, EC waits until AP power is ready before it notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized. When AP power is ready, PMIC should be ready as well. BUG=b:65839247,b:64944394 BRANCH=none TEST=Run reboot [/cold/ap-off] command on BJ and Type-C. Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b Reviewed-on: https://chromium-review.googlesource.com/672152 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Kahlee: Provide functionality for apshutdownAkshu Agrawal2017-09-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trigger the power press for shutdown. Also, avoid powering up the AP by checking if we are not in G3, before triggering the power press. BUG=b:66698593 TEST= > apshutdown [7045.198370 chipset_force_shutdown()] [7045.198870 PB PCH force press] [7045.199368 PB PCH pwrbtn=LOW] > LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c] [7049.218718 Pass through VGATE: 0] [7049.219281 power state 7 = S0->S3, in 0x000c] [7049.220647 chipset -> S3] [7049.221108 power state 2 = S3, in 0x000c] [7049.221763 power state 8 = S3->S5, in 0x000c] [7049.222522 USB charge p0 m0] [7049.223217 chipset -> S5] [7049.223716 power state 1 = S5, in 0x000c] [7049.224334 PB PCH force release] [7049.224840 PB PCH pwrbtn=HIGH] [7049.232875 SW 0x01] [7049.240557 TCPC p1 Low Power Mode] [7049.252249 TCPC p1 Low Power Mode] [7049.254363 TCPC p0 Low Power Mode] [7049.266006 TCPC p0 Low Power Mode] [7059.225553 power state 9 = S5->G3, in 0x000c] [7059.226188 chipset_force_shutdown()] [7059.226717 PB PCH force press] [7059.233871 PB PCH pwrbtn=LOW] [7059.234381 power state 0 = G3, in 0x000c] [7059.250255 power state 0 = G3, in 0x000f] [7059.256533 SW 0x05] Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://chromium-review.googlesource.com/683956 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: Provide chipset and board callbacks on host sleep event commandFurquan Shaikh2017-09-222-0/+23
| | | | | | | | | | | | | | | | This change allows chipset and board to perform any action when host indicates intention to enter sleep state. Chipset can take action like enable/disable power signal interrupts and boards can enable/disable decay of VRs on host intent to enter/exit S0ix. BUG=b:65732924 BRANCH=None TEST=make -j buildall Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/677498 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cleanup: Remove 'ryu' boardShawn Nematbakhsh2017-09-112-587/+0
| | | | | | | | | | | | | | | Remove 'ryu' and related ryu-only code. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: I19b966ea6964a7ed083724f7de80ae192235a406 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power/rk3399: fixes pp900_s0 for power timing v2Caesar Wang2017-09-111-0/+2
| | | | | | | | | | | | | | | | | | Due to the power timing v2 had defined the S3_USB_WAKE, We need enable the PP900_S0 for power timing v2. Fixes: 098bde322f567 ("power/rk3399: Don't turn off the pp900_s0 during s3") CQ-DEPEND=CL:647053 BRANCH=none BUG=b:65270978 TEST=build and bring up on scarlet board Change-Id: If8aedc03d54e9f4953ab994da426272137440d36 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/656858 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* power/rk3399: Don't turn off the pp900_s0 during s3Caesar Wang2017-09-071-4/+3
| | | | | | | | | | | | | | | The PP900_LOGIC can't be disabled for now, maybe we will disable it in later, since the ATF hadn't done it. In order to the suspend to resume function is fine, let's keep it first. BRANCH=none BUG=b:65270978 TEST=build and run the S2R stress tests on nefario board Change-Id: I932ee2b7667115df7516729f60faa71598f36d93 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/647053 Reviewed-by: Shawn N <shawnn@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-1/+1
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Fix wrong return state when POWER_S3S0 failedJeffy Chen2017-08-231-1/+1
| | | | | | | | | | | | | | | | | Currently we are returning POWER_S3S0 when POWER_S3S0 failed, which would cause dead loop. Return POWER_S0S3 instead to avoid that. BUG=b:64886507 TEST=build and boot Change-Id: Ia6567ee6edd399c0eb39e88006436753fa303507 Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/625637 Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Support non-INT power signal pinsPhilip Chen2017-08-171-0/+37
| | | | | | | | | | | | | | | | Optionally do polling for power signal pins which are not set as INT pins. BUG=b:64528567 BRANCH=none TEST=boot scarlet rev1 with a non-INT power signal pin Change-Id: I327753fcc0f1c6482c5f5eb3df28f67181b4eb62 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611649 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Fix the control of SYS_RST_LPhilip Chen2017-08-101-0/+1
| | | | | | | | | | | | | | | | We should assert SYS_RST_L during S5-to-S3 transition no matter which CHIPSET_POWER_SEQ_VERSION it is. BUG=b:63408169 BRANCH=none TEST=build nefario Change-Id: Ic792f3735db290b8750e4acee0d82d3d75e5d443 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/609324 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Fix inconsistent task function declarationsStefan Reinauer2017-08-081-1/+1
| | | | | | | | | | | | | | | Tasks are defined inconsistently across the code base. Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none TEST=make buildall -j, also verify kevin boots to OS BUG=none Change-Id: I19a076395a9a8ee1e457e67a89d80d2f70277c97 Reviewed-on: https://chromium-review.googlesource.com/602739 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Add CHIPSET_POWER_SEQ_VERSION == 3Philip Chen2017-07-291-11/+63
| | | | | | | | | | | | | | | | | | | This change is for Nefario rev0. Compared to version 1, we merge some pp900 power rails and disable power for some accessories in S3. Fixed the conflict with CL:572211. BUG=b:63408169 BRANCH=none TEST=build nefario Change-Id: Ibe67f86c8b51f7d1efd15d301692f63831a93876 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/588332 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* power/rk3399: Support USB wake in host-requested wakeable S3Shawn Nematbakhsh2017-07-281-6/+49
| | | | | | | | | | | | | | | | | | | | For boards with POWER_SEQUENCING_VERSION = 2 (and likely future versions), allow the host to request "wakeable suspend", which will leave rails enabled to allow wake-on-usb. BUG=b:63037490 BRANCH=kevin TEST=With subsequent commit, compile on scarlet w/ power sequencing version = 2. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaadd371b1d1509d185c8c8306b72760dcfe9989f Reviewed-on: https://chromium-review.googlesource.com/572211 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* CNL: Use SYS_RST_L for warm/cold chipset reset.Aseda Aboagye2017-07-252-18/+19
| | | | | | | | | | | | | | | | | | | | The EC cannot control warm vs cold reset of the chipset using the SYS_RST_L pin; it's just a reset request. This commit changes the behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a warm reset is requested. BUG=b:63508740 BRANCH=None TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that no panics or asserts are hit. Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/585573 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* S0ix: use both SLP_S0 interrupt and host command for s0ixJenny TC2017-07-242-28/+25
| | | | | | | | | | | | | | | | | | | | | | | | EC currently uses a host command from kernel to enter s0ix. This patch waits for the SLP_S0 interrupt to come after receiving the host command before entering S0ix. On the exit path, the SLP_S0 interrupt directly triggers the exit rather than waiting for the host command. BRANCH=none BUG=b:37443151 TEST=check in EC logs for SLP_S0 entry and powerindebug output, check suspend_stress_test on reef and soraka works fine, make -j8 buildall runs fine Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2 Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/513705 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power/rk3399: Assert SYS_RST_L from S5 to S3Philip Chen2017-07-201-1/+1
| | | | | | | | | | | | | | | | To fix a previous mistake and align the SYS_RST control for all rk3399 boards. BUG=b:62640322 BRANCH=none TEST=build scarlet with 'CHIPSET_POWER_SEQ_VERSION == 2' Change-Id: Iab91ea713c512afd10f15df38fbdb2dd6c62cb23 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/578306 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* zoombini: Add eSPI VW signals support.Aseda Aboagye2017-07-191-0/+1
| | | | | | | | | | | | | | | | | | This commit adds support for the virtual wire signals over eSPI. Additionally, the SLP_S0_L signal is added for the board and some minor changes are made to some GPIOs. BUG=None BRANCH=None TEST=flash zoombini image on npcx7 EVB with some modifications. Verify no panics or asserts are hit. Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/577054 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Use SYS_RESET signal to trigger warm and cold resetFurquan Shaikh2017-07-181-23/+12
| | | | | | | | | | | | | | | | RCIN# signal is known to not work properly for performing a warm reset when the CPU is in a bad state. This results in the common key combo (Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET signal instead to trigger both cold and warm chipset reset. BUG=chromium:721853 BRANCH=None TEST=make -j buildall Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/575947 Reviewed-by: Duncan Laurie <dlaurie@google.com>
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