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* Kindred: Add workaround for TI TPS51486RJER when system resumeDavid Huang2020-01-102-0/+13
| | | | | | | | | | | | | | | | Monitor GPIO PG_EC_ALL_SYS_PWRG was not trigger, when power on within 3 seond, EC will reset system. BUG=b:143440730 BRANCH=master TEST=check boot to OS was workable Change-Id: I19f2411a5369c75b6895316b791d077e2aee7deb Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948690 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com>
* icelake: Allow power good methods to be overiddenAseda Aboagye2020-01-082-4/+30
| | | | | | | | | | | | | | | | | | | | Jasperlake uses the same chipset driver as Icelake and the dedede reference design does not have a distinct pins for a couple of the power good signals. In order to accommodate this, this CL allows some of the power good signals to be overidden by a board specific implementation. These power good signals are PG_EC_DSW_PWROK and PG_ALL_SYS_PWRGD. BUG=b:147257114 BRANCH=None TEST=`make -j buildall` Change-Id: I3d889ed9d17bf224a69d1de188fe15933140d606 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1987836 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* puff: enable EFSPeter Marheine2020-01-071-0/+16
| | | | | | | | | | | | | | Configs mostly copied from fizz. TEST=booted on hardware, observed successful jump to RW. BRANCH=none BUG=b:146504182 Change-Id: Icf2925b92fea848efcd705bb5274d1afc91d2513 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1977079 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* puff: prevent AP boot when there isn't enough powerPeter Marheine2019-12-313-37/+61
| | | | | | | | | | | | | | | The common x86 state machine does this, but the EC-controlled sequencing did not. Since trying to boot the AP without enough power will cause the system to brown out, we need to do it too. TEST=boot prevented on hardware BRANCH=none BUG=b:146515963 Change-Id: I7dbe6ab962fbe47d4d866be98d4174291c757c72 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980104 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* power: add support for Jasperlake chipsetDivagar Mohandass2019-12-252-2/+2
| | | | | | | | | | | | | | | | | | - Jasperlake power sequencing flow is same as Icelake - Rename CONFIG_CHIPSET_ICL_TGL as CONFIG_CHIPSET_ICELAKE to avoid duplicate code - define CONFIG_CHIPSET_ICELAKE on CONFIG_CHIPSET_JASPERLAKE or CONFIG_CHIPSET_TIGERLAKE BRANCH=none BUG=b:146693933 TEST=make buildall -j Change-Id: I25f43d85fcfc7fbbfe06787e5a201983c0e49cc7 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980090 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Trogdor: Remove VBOB rail controlWai-Hong Tam2019-12-101-4/+2
| | | | | | | | | | | | | | The VBOB rail is for backup only. Verified the hardware that it works without this rail. Should be OK to remove the control of it. BRANCH=None BUG=b:143616352 TEST=Verified AP power on and power off. Change-Id: I9632d881b590482a07482e23aba88bc7ffec4521 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955108 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* Trogdor: On startup, turn off the system without checkWai-Hong Tam2019-12-101-4/+17
| | | | | | | | | | | | | | | | | | | | | The original check in the init hook (power_chipset_init) may cause watchdog reset, as the init hook is earlier than the task execution that we should not perform any long action, like waiting for a signal in our case. We should simply turn off the switchcap without any check. In most of the common cases (except flashing EC/AP), the switchcap should be off and the check is unnecessary. BRANCH=None BUG=b:145843686 TEST=Performed flashing EC and AP, EC watchdog reset not seen. Change-Id: I36873e773800def7e3dfceaec28c294dee9a09c7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955107 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* EC: Implementation for AP reboot from G3 state using ectool command.Sooraj Govindan2019-12-101-1/+17
| | | | | | | | | | | | | | | | | | | | The new ectool command 'ectool reboot_ap_on_g3' will reboot AP from G3 state on initiation of DUT shutdown. Thus eliminating the dependency of servo to trigger wake events when testing AP cold boot cycles. BUG=b:129507479 BRANCH=None TEST=Tested on hatch board. From Kernel console, entered the below commands: $ectool reboot_ap_on_g3 $shutdown -h now Observed AP boots back to S0 upon G3. Change-Id: Ie6fcbd2f00eb6c22ed498ab82dac53132dbbf4a3 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918993 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* power/mt8183: correct EN_PP1800_S5_L enable timingYilun Lin2019-12-101-0/+31
| | | | | | | | | | | | | | | | The power rail should be turned on at G3S5 rather than S5S3, and should be turned off after stay in G3 for 20ms. TEST=Ensure the power rail is on/off at correct timing BUG=b:144144075 b:145255107 BRANCH=none Change-Id: Ie621ab1ac5332da6718201c44266f41aafcac296 Signed-off-by: Yilun Lin <yllin@chromium.org> Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928413 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* power/cometlake-discrete: implement power sequencingstabilize-12748.B-masterPeter Marheine2019-12-102-89/+262
| | | | | | | | | | | | | | | | | | | | | A first go at the power sequencing needed for Puff. This abuses the Intel common power code a little bit because we don't actually have all the inputs it assumes, but that seems preferable to replacing it wholesale. The one limitation right now is inability to detect transitions on the rails that we only have analog monitoring on; either we need to design a way to monitor those, or decide that detecting dropouts on those rails is unimportant. BUG=b:143188569 TEST=still builds BRANCH=None Change-Id: Ia960f5dd2ccfb1ca2c7d4107ba4e3737adc8f69f Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925787 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Trogdor: Initial board commitWai-Hong Tam2019-11-222-0/+881
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial commit for Trogdor. Use Cheza as a baseline. Make the change according to the schematic, e.g. * Reflect the GPIO change * Reflect the TCPC/PPC part change * Update the USB topology, e.g. no device mode support * Remove the detachable related code * Add keyboard support * Support keyboard backlight * Update the battery characteristic * Add initial support of muxing DP path * Support a single USB-A port * Change sensors from lid to base * Minor code style improvement BRANCH=None BUG=b:143616352 TEST=BOARD=trogdor make Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* Create cometlake-discrete power driverPeter Marheine2019-11-184-0/+277
| | | | | | | | | | | | | | This sets up the driver (mostly copied from cometlake for now), to be used by puff. BUG=b:143188569 TEST=make buildall still succeeds BRANCH=none Change-Id: I4a4b70dd8ba58c070e2c6ad5941911bab16bafe6 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906391 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* icelake/tigerlake: add option to enable PP3300 before PP5000Keith Short2019-11-151-11/+20
| | | | | | | | | | | | | | | On Volteer, to avoid leakage from PP3300_A rail to PP5000 rail, turn on the PP3300 rail before PP5000. BUG=none BRANCH=none TEST=make buildall -j TEST=verify Volteer transitions to S0 Change-Id: Ic86f97dbdde6d6c904fe7efc8b0edc1ead727cf6 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918603 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* icelake/tigerlake: Add debug for setting main railsKeith Short2019-11-151-8/+16
| | | | | | | | | | | | | | | Add additional debug output for Ice Lake and Tiger Lake power sequencing when the CONFIG_BRINGUP option is enabled. BUG=none BRANCH=none TEST=make buildall TEST=Verify debug messages on Volteer when CONFIG_BRINGUP is enabled. Change-Id: I80fc23f470818af7a4dad73a7ad77bc9ba42d537 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918602 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* power/mt8183: Need 1s pwrbtn press to exit off stateYilun Lin2019-11-111-6/+18
| | | | | | | | | | | | | | | | | | To prevent mispressed cases, we decide to increase the power button press boot time to at least 1s. TEST=aps; powerbtn $sec; where $sec is between 0~1000 and see it won't boot TEST=aps; powerbtn $sec; where $sec > 1000 and see it boot TEST=aps; ensures the physical power button press is working as expected. BUG=b:131856041 BRANCH=kukui Change-Id: Ie3099ba9639a729cee77b7d444a459fbef72733d Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906387 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-012-18/+53
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* cometlake: cleanup power signal namesKeith Short2019-10-312-23/+24
| | | | | | | | | | | | | | | Add X86 prefix to the Comet Lake signals names for consistency with other Intel APs. BUG=none BRANCH=none TEST=make buildall Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-2/+5
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* icelake: Cleanup GPIO_PCH_DSW_PWROKKeith Short2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | Change GPIO_EC_PCH_DSW_PWROK to GPIO_PCH_DSW_PWROK to match convention for EC to PCH signals used by other Intel processors (specifically cannonlake already used GPIO_PCH_DSW_PWROK). BUG=none BRANCH=none TEST=buildall -j Change-Id: I59fb8d3ee3867c70dde74c186ba3974490c3cd27 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848252 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* cometlake: Cleanup GPIO_PCH_SYS_PWROKKeith Short2019-10-151-3/+3
| | | | | | | | | | | | | | | | | | | | Change GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK on cometlake to conform with naming convention used on other Intel processors. Leave gpio.inc files unchanged and add a mapping from GPIO_EC_PCH_SYS_PWROK to GPIO_PCH_SYS_PWROK in the board files. BUG=none BRANCH=none TEST=make buildall -j TEST=boot kohaku Change-Id: I722cb06dd90ee5d7e426664508f54a5cbe19de4a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1848251 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* cometlake/icelake: cleanup GPIO_PCH_RSMRST_LKeith Short2019-10-152-2/+2
| | | | | | | | | | | | | | | | | | | | | Replaced references of GPIO_EC_PCH_RSMRST_L with GPIO_PCH_RSMRST_L in to match convention used in common Intel power sequencing. Boards still use GPIO_EC_PCH_RSMRST_L in their gpio.inc files to match schematic net names. BUG=none BRANCH=none TEST=buildall -j TEST=boot kohaku (cometlake device) TEST=run "apshutdown" on kohaku Change-Id: Ic9fa13dbf2d4e6c8953b82a9dd20f48a6cf8d2c8 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846690 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* power: Fix CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS checksKeith Short2019-10-111-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | Regardless of the state of CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS, if CONFIG_HOSTCMD_ESPI is enabled, then the AP can still generate virtual wire interrupts. Replace checks of CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS for power signals with CONFIG_HOSTCMD_ESPI. This fixes a processor exception that was caused by siglog_add() when the AP generated a virtual wire interrupt. The VW signals start at GPIO_COUNT so were causing buffer overflows of gpio_list[]. BUG=b:142406787 BRANCH=none TEST=buildall -j TEST=Enable CONFIG_BRINGUP on kohaku. Without change RO causes processor exception, with change RO and RW boots and AP boots. Change-Id: I81ab6f2fed217f5aad3ca7fae64c850e3af49f43 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1850275 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* jacuzzi: disable PP1800 when chipset offTing Shen2019-10-081-0/+2
| | | | | | | | | | | | | | | | | To improve G3 power consumption, a pin EN_PP1800_S5_L is added in board rev 1 and should be turned on before pmic on, and turned off after pmic off. BUG=b:138180455,b:141592177 TEST=verify jacuzzi rev 1 is bootable with this change BRANCH=master Change-Id: Iacd9b0fab97d775f15faa9b2df491940871bc7ff Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1773031 Reviewed-by: Yilun Lin <yllin@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* printf: Convert %l to %llEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | In order to make our printf more standard, utilize %ll for long long arguments, rather than %l. This does cost a little bit in flash space for that extra l in a couple of places, but enables us to turn on compile-time printf format checking. For this commit only, the semantics are such that both %l and %ll take 64-bit arguments. In the next commit, %l goes to its correct behavior of taking a sizeof(long) argument. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029 Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-022-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* volteer: Add RTC resetKeith Short2019-09-292-6/+9
| | | | | | | | | | | | | | | Add support for the RTC reset on Volteer. This change also deduplicates the board_rtc_reset() function which was identical on boards that enabled CONFIG_BOARD_HAS_RTC_RESET. BUG=b:141321096 BRANCH=none TEST=make buildall Change-Id: Ifc6959f8271400174fd4999a3c70800b03b9c2d0 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816869 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cometlake: Remove TODO comment from chipset_force_shutdownScott Collyer2019-09-121-4/+0
| | | | | | | | | | | | | | | | | | There was a todo to replace a while loop with a call to power_wait_signals_timeout. However, using that function is not feasible in this case as it's only intended to check for power signals that are high. Removing the TODO comment since it's not applicable. BUG=b:122264541 BRANCH=None TEST=make BOARD=hatch Change-Id: I0dca060f8a8e00bc99a433d78dd55d262a867cb1 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1783521 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* cutoff: ensure logs are flushed before cut-offYilun Lin2019-09-101-0/+2
| | | | | | | | | | | | | | Logs may not appear in the console without flush if battery been cut-off. TEST=See the logs are flushed to console before cutoff BRANCH=None BUG=None Change-Id: I73363856c50dea1ec409b8041d96227d6538bcc3 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772863 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power: Add power sequencing logic for Tigerlake chipsetVijay Hiremath2019-09-052-2/+2
| | | | | | | | | | | | | | Power sequencing logic for Tigerlake is same as Icelake hence reusing the Icelake code. BUG=b:140508849 BRANCH=none TEST=tglrvp can boot to S0 Change-Id: Id218422146e5549aa5b246ddbcaedd8e442e376b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1785685 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cometlake: Minimize delay for high->low rsmrst passthroughScott Collyer2019-09-041-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hatch designs buffer the PG_EC_RSMRST# signal from the Silego power good logic through the EC and out EC_PCH_RSMRST# to the SoC RSMRST# pin. For power off transitions, this should be as fast as possible, in the ns region if possible. However this time is ~1 msec. To reduce this delay as much as possible this CL introduces a new interrupt handler than can be linked to the rsmrst gpio signal. This interrupt routine handles high->low transitions directly to minimize the propagation delay. The power_signal_interrupt is then called which will wake up the chipset task, and low->high transistions continue to be handled in the power state machine. BUG=b:132421681 BRANCH=None TEST=Shorted PP1050_A_PG to ground to force an abrupt power down and then measured time via scope between PG_EC_RSMRST and EC_PCH_RSMRST. The delay is reduced from ~1 msec to 45 uSec. Change-Id: I266138a2e235ce47f3060f8e1f6f9bc6a75073ae Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757267 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-266-25/+26
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power: Make HC host_sleep_event independent from power common.Yilun Lin2019-08-233-71/+79
| | | | | | | | | | | | | | | | | | host_sleep_event provides the AP power state information to EC, and this is not necessary bound to CONFIG_POWER_COMMON. This CL moves the HC out of CONFIG_POWER_COMMON. TEST=1. make buildall -j 2. #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE kukui_scp, and see it build successfully. BUG=b:136240895 BRANCH=none Cq-Depend: chromium:1760656 Change-Id: I5555c7ba8b97547ce9fc0ff8e2bff14ef3da8fe7 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753563 Reviewed-by: Jett Rink <jettrink@chromium.org>
* power: Replace weak attr with __overridableYilun Lin2019-08-222-12/+10
| | | | | | | | | | | | | | | | | This CL annotates __overridable to the following functions: board_system_is_idle power_chipset_handle_host_sleep_event power_board_handle_host_sleep_event TEST=make buildall BUG=none BRANCH=none Change-Id: I0168b69c49fab5672238711d4f3a6a5517cdd8b3 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1761759 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* EC: Do not drop SCI events responsible for wake.Ravi Chandra Sadineni2019-08-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC currently clears all events(main copy of hostevents) on every resume. This seems to be added to clear events that are only part of wake mask and not part of SCI mask as they can stick and cause premature wake on next suspend. This patch stops clearing events that are part of SCI mask from the main copy as ACPI subsystem will query and clear them on resume anyway. This helps kernel to identify the reason for wake if it caused by events that are part of SCI mask. Previously coreboot used to depend on main copy to log wake reason. i.e on every resume coreboot used to query and log and clear the wake reason by reading all events from the main copy. Since this also comes in way of kernel in identifying the wake reason, this change also sets up events_copy_b for coreboot by clearing it on every suspend entery. More details can be found at http://go/hostevent-refactor. BUG=b:133262012, b:65976859 BRANCH=None TEST=Tested suspend/resume with wakeup count on hatch and grunt. Change-Id: I0fac250d4dac49af960b29e8b0e28841af2ef509 Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1717498 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Trembyle: Add chipset_handle_espi_reset_assert codeDenis Brockus2019-08-141-7/+19
| | | | | | | | | | | | | | | Added code for chipset_handle_espi_reset_assert. Fixed a couple #ifdef conditions using IS_ENABLED BUG=b:138600676 BRANCH=none TEST=make buildall -j Change-Id: I937ba3522d268b9151a4ed5134425e8b6a03796a Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1750801 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Zork: Change host_cmd to be ESPIDenis Brockus2019-07-291-1/+5
| | | | | | | | | | | | | | | | | | | This functionality requires a chipset_handle_espi_reset_assert to be defined. I created on in power/stoney.c but it is not filled in for what is needed. Not sure anything needs to be done but leaving a placeholder to make sure to follow up for verification. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I4c21e75c0ed7cafbc7f2058e9bd3c36bc8314c3a Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1721517 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* power/mt8183: Re-enable watchdog interrupt after sysjumpNicolas Boichat2019-06-251-1/+2
| | | | | | | | | | | | | | | | | Without this, watchdog reset is not detected properly by the EC after software sync. BRANCH=none BUG=b:132938532 TEST=Boot kukui with SW sync enabled stop daisydog echo 1 > /dev/watchdog Board reboots after ~30 seconds (and does not get stuck) Change-Id: Ia33f5f2b2b610d921ef36874226d23ed09b2f793 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663542 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power/mt8183: Hold PMIC enable to force S5->G3 transition.Nicolas Boichat2019-06-241-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Asserting VSYSSNS should only be done as a last measure. If the PMIC is configured properly, it will shut down upon holding POWER+HOME key for 8+ seconds. This is shorter than the S5->G3 timeout, so we should never need to assert VSYSSNS. BRANCH=none BUG=b:134912821 TEST=reboot ap-off, immediately powerb, see that AP turns on and stays on. TEST=apshutdown, PMIC shuts off gracefully TEST=In power/common.c, change S5_INACTIVITY_TIMEOUT to 3 seconds, see that state machines forces PMIC off using VSYSSNS. TEST=Boot DUT: mosys eventlog clear; poweroff power on DUT, run dut-control power_state:off Wait 8 seconds for EC to go to G3, power on DUT again mosys eventlog list shows events with correct time stamps: 0 | 2019-06-14 15:44:31 | Log area cleared | 79 1 | 2019-06-14 15:44:38 | System boot | 0 2 | 2019-06-14 15:44:38 | Chrome OS Developer Mode 3 | 2019-06-14 15:45:13 | System boot | 0 4 | 2019-06-14 15:45:13 | Chrome OS Developer Mode Change-Id: I9b73d06e07296e47e15fe87dd87fffac2af04d12 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660073 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* intel_x86: Use common code to get power signal's levelVijay Hiremath2019-06-202-7/+2
| | | | | | | | | | | | | | | Removed redundant code in intel_x86 and reusing the common code for getting power signal's level. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I9cd550a2326456189a087459aeb8e6c88a8cad8e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1667647 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Remove extraneous new line as the end of CPRINTS stringsNicolas Boichat2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CPRINTS already prints a new line, no need to add another one. Spotted during boot on kukui, and then realized there are many more instances: "" [3.689239 Module 7 is not supported for clock disable ] "" BRANCH=none BUG=none TEST=make buildall -j TEST=`git grep CPRINTS | grep "\\\\n\""` shows nothing of interest. Change-Id: I4d2bbbc65a91fa56c6e6115aa5c353bfd2b384a1 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660519 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-196-6/+6
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* power/mt8183: Stay in S5 for 10 seconds before forcing PMIC shutdownNicolas Boichat2019-06-171-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On forced/emergency shutdown, the EC is only able to force the PMIC off by asserting GPIO_PMIC_FORCE_RESET_ODL, which also loses the RTC state. And it does so immediately after transitioning to S5. This causes issues with FAFT, as the RTC resets to original time. Instead, wait for 10 seconds in S5 before forcing the transition to G3, which is what other platforms do, and only force the reset at that time. BRANCH=none BUG=b:134912821 TEST=apshutdown => System stays in S5 for 10 seconds before force shutdown. TEST=apshutdown => powerb wakes the system in both S5 and G3 TEST=apshutdown; reboot ap-off in S5 still waits 10 seconds to force shutdown to G3. TEST=poweroff in AP console works, directly goes to G3, and powerb wakes the system TEST=Boot DUT: mosys eventlog clear; poweroff power on DUT, run dut-control power_state:off Within 10 seconds, power on DUT again mosys eventlog list shows events with correct time stamps: 0 | 2019-06-14 15:40:10 | Log area cleared | 55 1 | 2019-06-14 15:40:24 | System boot | 0 2 | 2019-06-14 15:40:24 | Chrome OS Developer Mode 3 | 2019-06-14 15:40:58 | System boot | 0 4 | 2019-06-14 15:40:58 | Chrome OS Developer Mode Change-Id: I7495950da58179fc066608d804e263c81b0993aa Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660070 Reviewed-by: Yilun Lin <yllin@chromium.org>
* power/mt8183: Clarify comment about force PMIC shutdownNicolas Boichat2019-06-171-2/+3
| | | | | | | | | | | | | | | | | | It turns out MT6358 cannot be configured to shut down when receiving WATCHDOG input, so the statement in the comment is incorrect. However, it is still correct to say that forcing PMIC shutdown should be rare. And add a note that PMIC RTC state will be lost. BRANCH=none BUG=b:109850749, b:134912821 TEST=none Change-Id: I7c84b012d7095fb94473303c83b4ffecb01ee5da Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657074 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* intel_x86: Report S0ix hang detected by EC using console printFurquan Shaikh2019-06-141-0/+1
| | | | | | | | | | | | | | | | | | | | | This change prints out a warning indicating that S0ix hang is detected by EC. This is very helpful when debugging S0ix issues to understand when exactly the EC triggered the wake because of hang detect. BUG=b:134781711 BRANCH=None TEST=Verified on a system stuck before going into S0ix that EC prints out the warning when waking host up because of hang detect. Change-Id: I73c64dc675ed8c4d35ca891fdc5de3e7e8449437 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660014 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Auto-Submit: Furquan Shaikh <furquan@chromium.org>
* intel_x86/power: Consolidate chipset specific power signals arrayVijay Hiremath2019-06-1311-27/+240
| | | | | | | | | | | | | | | Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* icelake: Add option to turn-off 5V-rail in power sequencingVijay Hiremath2019-06-111-0/+14
| | | | | | | | | | | | | | | | | | | Need to enable or disable the 5V-rail in power sequencing to support boards with 5V-rail. This CL is a derivative of Cometlake CL. Change-Id: Ia1acd5a592f60973a3b852a987e93283f10d0ac0 Reviewed-on: https://chromium-review.googlesource.com/1503956 BUG=b:134688223 BRANCH=none TEST=Able to control 5V-rail of ICLRVP Change-Id: Iefaa1091e863c1c431ea784d2e02478ce67f8911 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647369 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cml: Remove while loop to check for PP5000_A_PG signalScott Collyer2019-05-242-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cometlake is sequencing from G3->S5, the 5000_A rail is enabled. After enabling the 5000_A rail there was a while() loop to wait for the 5000_A rail to go high. If for some reason this rail did not go high, then it would just loop there until a watchdog reset. This CL removes this while loop check and instead modifies the macro CHIPSET_G3S5_POWERUP_SIGNAL to include the PP5000_A_PG signal. The common intel_x86 power sequencing code already has a check just after the call to chipset_pre_init_callback. BUG=none BRANCH=none TEST=Manual If no battery is present and the bq25710 reset register bit is set, then PPVAR_VSYS gets set to ~4V which is not high enough to generate PP5000_A rail. In this state the EC would consistently watchdog loop when just as AP power sequencing was initiated by the EC. Verified with this CL, that while the PP5000_A rail still doesn't come up, that the EC no longer hits a watchdog and power signal failure is logged in the EC console. Change-Id: I02aab7ed4f4723ec0d3ae04e4b8093494877615f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1599674 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power: Manipulate wake mask during s0ix timeoutsEvan Green2019-05-082-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | When S0ix failure detection is enabled and a timeout occurs such that the SLP_S0 line never actually toggles, then s0ix_transition_timeout() sets the HANG_DETECT event bit. This doesn't quite work in this scenario, since the wake mask is only enabled when the power state transitions to S0ix, which happens when the SLP_S0 line toggles. So the AP never sees the event, since it's not in the wake mask and so never causes the EC->AP interrupt line to change. Detect this situation in the timeout function, and explicitly move the wake mask to its S0ix value so that when the event bit is set, (if it is in the wake mask), the system will wake up. Doing this forcefully gets the wake mask out of sync with the power state. So upon resume, explicitly restore the wake mask to its S0 state. BUG=b:131434497 BRANCH=none TEST=suspend_stress_test -c1 --suspend_min=60 with a firmware where S0ix fails. Change-Id: Id2e67c6933a7895fba85ccfdff9b336629eabf24 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592469 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* 7-seg display: Add config to display port80 msg and power statesAyushee2019-05-031-0/+3
| | | | | | | | | | | | | | | | | Adding this CL to display port80 message and power states of EC & SOC on the 7-segment display. BRANCH=None BUG=b:130738086 TEST=Manually tested on intelrvp, able to verify the power states and port80 message displayed on the 7 segment display Change-Id: I4437cfcd60662c8637e406e425f98fad1a4ba7ed Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1575433 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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