| Commit message (Collapse) | Author | Age | Files | Lines |
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Created Meowth symbolic link to Zoombini.
Modified Zoombini gpio.inc and board, etc. files to
compile a Meowth EC image with the correct gpios.
BUG=b:69133424
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/762039
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271.
This is required to ensure that PMIC VR decay is enabled before
SLP_S0# is asserted. Else, the setting does not take effect and hence
results in higher power consumption.
BUG=b:69337192
BRANCH=None
TEST=make -j buildall
Change-Id: I6885e7447277d853a2414be299dfea25f5547df4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771054
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change chipset_force_shutdown() to not call power_button_pch_press()
when called from POWER_S5G3 state, so that we don't set pwrbtn=LOW
when entering G3.
BUG=b:68760602
BRANCH=none
TEST=push kahlee power button
Change-Id: I931fc73f2386f8124f1e082cccb095e3863cbb99
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/752682
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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power_board_handle_host_sleep_event was added to allow boards like
poppy to enable/disable PMIC VR decay only once during S0ix
entry/exit. Now that the chipset hooks have been fixed, there is no
need of this board specific callback. If in the future, there is a
need to have such a callback, this change can be reverted.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to
reinitialize S0ix flag, add a new default state
HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of
the code to take correct action depending upon the state that is
currently triggered.
BUG=None
BRANCH=None
TEST=Verified that SLP_S0# interrupt doesn't get asserted during
runtime S0ix.
Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The 5V power good signal is being removed from the PMIC power good tree,
however, if the 5V power good is not asserted, we should not try booting
to S0. This is because the 1050_STG rail load switch is powered off of
the 5V rail.
Since wireless power control is being moved to the AP, these pins are now
repurposed to control the PMIC enable and for the 5V power good signal.
This commit adds the 5V power good pin to the EC and makes it a required
power signal for S0.
BUG=b:66000679
BRANCH=None
TEST=make -j buildall
TEST=flash zoombini; Verify EC boots up okay.
Change-Id: I8924320030a00b8808aea27fb668451e6e41d590
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736312
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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There is a fundamental difference in host behavior w.r.t. S3 and
S0ix. When the host enters S3, it asserts the SLP_S3# signal until it
is woken back up. Thus, EC depends on the SLP_S3# signal state to
decide when to notify listeners about CHIPSET_SUSPEND and
CHIPSET_RESUME state.
With S0ix, SLP_S0# signal is asserted whenever host enters
S0ix. However, periodically (every 8 seconds), the host wakes up for
some bookkeeping activities, but does not come out of the low power
mode completely. This bookkeeping activity takes ~2-5 ms and the host
goes back into S0ix state. Because of this periodic activity, SLP_S0#
signal is de-asserted and asserted back every 8 seconds.
Thus, if the power state machine depends solely on the SLP_S0# signal
to notify CHIPSET_SUSPEND and CHIPSET_RESUME states, then all the
listeners would be performing unnecessary actions every 8
seconds. This leads to a number of side-effects including:
1. Dual-role toggle being enabled and disabled every 8 seconds.
2. Power spikes in EC power consumption during S0ix every 8 seconds.
In order to avoid the side-effects of periodic host activity in S0ix,
this change adds a new flag s0ix_notify, which is set based on the
notifications that are pending based on host sleep event.
On receiving host sleep event for S0ix suspend, s0ix_notify will be
set to S0IX_NOTIFY_SUSPEND. Next, whenever SLP_S0# is asserted,
power_state machine notifies listeners of CHIPSET_SUSPEND
and resets s0ix_notify flag to S0IX_NOTIFY_NONE. Thus, all future
assertions of SLP_S0# do not result in the suspend notification.
Similarly, on resume, power_state machine will not notify
CHIPSET_RESUME on SLP_S0# deassertion. Instead the host sleep event
for S0ix resume will set s0ix_notify flag to S0IX_NOTIFY_RESUME and
wake chipset task. The power state machine in turn will notify
listeners of the resume event and reset s0ix_notify flag.
BUG=b:65356050,b:67750352
BRANCH=None
TEST=Verified that the CHIPSET_SUSPEND/CHIPSET_RESUME notification
happens only once during a system suspend/resume cycle. Periodic host
wakes for book-keeping activities do not result in
CHIPSET_SUSPEND/CHIPSET_RESUME notifications.
Change-Id: Idf253b9393a0c25ff2eac63c60ddbcd3af954818
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/729478
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For certain cannonlake designs, the 5V rail can be controlled by both
the chipset task as well as other tasks such as the USB charger tasks to
perform BC1.2 detection. This commit introduces an API that allows the
tasks to enable/disable the 5V rail. Enable requests will immediately
enable the rail, however, attempting to disable the rail will only
result in a request. Once all tasks want to turn off the 5V rail, the
rail will be turned off.
A bitmask is introduced to keep track of the requests. Index 0 is for
the chipset task.
All of this is gated behind a config option:
CONFIG_POWER_PP5000_CONTROL
BUG=b:65991615
BRANCH=None
TEST=With other zoombini code, verify that 5V can be enabled and disabled.
Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/722322
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Instead of clearing out all the host events on S0ix wake, provide an
opportunity to the host to read the events and log it. Move the call
to clear events to the point where host sends a command indicating
exit from S0ix.
BUG=b:67874513
BRANCH=None
TEST=make -j buildall. Verified that host events are cleared by the
host during logging.
Change-Id: I339dc70d761bb851286d98c5c20094ccaefd238f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/724188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of duplicating the handling of host events and host event
masks in chip lpc drivers, add routines in common code to provide
basic functions like setting/getting of masks, setting/getting of
events and handling of masks transitions across sysjump.
BUG=None
BRANCH=None
TEST=make -j buildall. Verified following:
1. Event masks are correctly retained across sysjumps.
2. Wake from S3 works fine.
3. Wake from S0ix works fine.
4. SCI generated correctly.
Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/707771
Reviewed-by: Shawn N <shawnn@chromium.org>
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Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Any time the host sleep state is updated (including reset of host
sleep state), make a callback into
power_chipset_handle_host_sleep_event to allow mainboard and chipset
to take any necessary action.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Ib4d35fa0b417500090361e4e26415feedb663e35
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a new flag to allow boards to indicate if a power signal has to be
enabled/disabled at boot.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Ibe7ab74e8191c58433087d8024b344d7e845f17e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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1. Make power_signal_enable_interrupt visible outside power/common.c
2. Add corresponding power_signal_disable_interrupt function.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: I04b7b053cc1ffe978fcbac5b2cb746d21b198aa2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679980
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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On proto3, PMIC isn't powered on POR, thus board_pmic_init fails.
With this change, EC waits until AP power is ready before it
notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized.
When AP power is ready, PMIC should be ready as well.
BUG=b:65839247,b:64944394
BRANCH=none
TEST=Run reboot [/cold/ap-off] command on BJ and Type-C.
Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b
Reviewed-on: https://chromium-review.googlesource.com/672152
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Trigger the power press for shutdown. Also, avoid powering up the AP
by checking if we are not in G3, before triggering the power press.
BUG=b:66698593
TEST=
> apshutdown
[7045.198370 chipset_force_shutdown()]
[7045.198870 PB PCH force press]
[7045.199368 PB PCH pwrbtn=LOW]
> LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c]
[7049.218718 Pass through VGATE: 0]
[7049.219281 power state 7 = S0->S3, in 0x000c]
[7049.220647 chipset -> S3]
[7049.221108 power state 2 = S3, in 0x000c]
[7049.221763 power state 8 = S3->S5, in 0x000c]
[7049.222522 USB charge p0 m0]
[7049.223217 chipset -> S5]
[7049.223716 power state 1 = S5, in 0x000c]
[7049.224334 PB PCH force release]
[7049.224840 PB PCH pwrbtn=HIGH]
[7049.232875 SW 0x01]
[7049.240557 TCPC p1 Low Power Mode]
[7049.252249 TCPC p1 Low Power Mode]
[7049.254363 TCPC p0 Low Power Mode]
[7049.266006 TCPC p0 Low Power Mode]
[7059.225553 power state 9 = S5->G3, in 0x000c]
[7059.226188 chipset_force_shutdown()]
[7059.226717 PB PCH force press]
[7059.233871 PB PCH pwrbtn=LOW]
[7059.234381 power state 0 = G3, in 0x000c]
[7059.250255 power state 0 = G3, in 0x000f]
[7059.256533 SW 0x05]
Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://chromium-review.googlesource.com/683956
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change allows chipset and board to perform any action when host
indicates intention to enter sleep state. Chipset can take action like
enable/disable power signal interrupts and boards can enable/disable
decay of VRs on host intent to enter/exit S0ix.
BUG=b:65732924
BRANCH=None
TEST=make -j buildall
Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/677498
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove 'ryu' and related ryu-only code.
BUG=None
TEST=`make buildall -j`
BRANCH=None
Change-Id: I19b966ea6964a7ed083724f7de80ae192235a406
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656314
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Due to the power timing v2 had defined the S3_USB_WAKE,
We need enable the PP900_S0 for power timing v2.
Fixes: 098bde322f567 ("power/rk3399: Don't turn off the pp900_s0 during s3")
CQ-DEPEND=CL:647053
BRANCH=none
BUG=b:65270978
TEST=build and bring up on scarlet board
Change-Id: If8aedc03d54e9f4953ab994da426272137440d36
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/656858
Tested-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
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The PP900_LOGIC can't be disabled for now, maybe we will disable it in
later, since the ATF hadn't done it.
In order to the suspend to resume function is fine, let's keep it first.
BRANCH=none
BUG=b:65270978
TEST=build and run the S2R stress tests on nefario board
Change-Id: I932ee2b7667115df7516729f60faa71598f36d93
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/647053
Reviewed-by: Shawn N <shawnn@chromium.org>
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This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also
adds the macro to config.h.
BUG=none
BRANCH=none
TEST=make buidlall
Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/639955
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Currently we are returning POWER_S3S0 when POWER_S3S0 failed, which
would cause dead loop.
Return POWER_S0S3 instead to avoid that.
BUG=b:64886507
TEST=build and boot
Change-Id: Ia6567ee6edd399c0eb39e88006436753fa303507
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/625637
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Optionally do polling for power signal pins
which are not set as INT pins.
BUG=b:64528567
BRANCH=none
TEST=boot scarlet rev1 with a non-INT power signal pin
Change-Id: I327753fcc0f1c6482c5f5eb3df28f67181b4eb62
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611649
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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We should assert SYS_RST_L during S5-to-S3 transition
no matter which CHIPSET_POWER_SEQ_VERSION it is.
BUG=b:63408169
BRANCH=none
TEST=build nefario
Change-Id: Ic792f3735db290b8750e4acee0d82d3d75e5d443
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/609324
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Tasks are defined inconsistently across the code base.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
TEST=make buildall -j, also verify kevin boots to OS
BUG=none
Change-Id: I19a076395a9a8ee1e457e67a89d80d2f70277c97
Reviewed-on: https://chromium-review.googlesource.com/602739
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This change is for Nefario rev0.
Compared to version 1, we merge some pp900 power rails and
disable power for some accessories in S3.
Fixed the conflict with CL:572211.
BUG=b:63408169
BRANCH=none
TEST=build nefario
Change-Id: Ibe67f86c8b51f7d1efd15d301692f63831a93876
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/588332
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
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For boards with POWER_SEQUENCING_VERSION = 2 (and likely future
versions), allow the host to request "wakeable suspend", which will
leave rails enabled to allow wake-on-usb.
BUG=b:63037490
BRANCH=kevin
TEST=With subsequent commit, compile on scarlet w/ power sequencing
version = 2.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaadd371b1d1509d185c8c8306b72760dcfe9989f
Reviewed-on: https://chromium-review.googlesource.com/572211
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
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The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request. This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.
BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.
Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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EC currently uses a host command from kernel to enter s0ix.
This patch waits for the SLP_S0 interrupt to come after receiving
the host command before entering S0ix.
On the exit path, the SLP_S0 interrupt directly triggers the
exit rather than waiting for the host command.
BRANCH=none
BUG=b:37443151
TEST=check in EC logs for SLP_S0 entry and powerindebug output,
check suspend_stress_test on reef and soraka works fine,
make -j8 buildall runs fine
Change-Id: Ie5507b7a1e723532f07bc0671c2abd364f6224a2
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/513705
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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To fix a previous mistake and align the SYS_RST control
for all rk3399 boards.
BUG=b:62640322
BRANCH=none
TEST=build scarlet with 'CHIPSET_POWER_SEQ_VERSION == 2'
Change-Id: Iab91ea713c512afd10f15df38fbdb2dd6c62cb23
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/578306
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This commit adds support for the virtual wire signals over eSPI.
Additionally, the SLP_S0_L signal is added for the board and some minor
changes are made to some GPIOs.
BUG=None
BRANCH=None
TEST=flash zoombini image on npcx7 EVB with some modifications. Verify
no panics or asserts are hit.
Change-Id: I6ada270b3e3fc7e24b28a8da6ee9dcde707414fc
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/577054
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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RCIN# signal is known to not work properly for performing a warm reset
when the CPU is in a bad state. This results in the common key combo
(Alt-Volup-r) not working to reset the host. Thus, use SYS_RESET
signal instead to trigger both cold and warm chipset reset.
BUG=chromium:721853
BRANCH=None
TEST=make -j buildall
Change-Id: I38663db96767d0aa03cd1aea0fe2a0cc5b771cd2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/575947
Reviewed-by: Duncan Laurie <dlaurie@google.com>
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BUG=b:62640322, b:62269890
BRANCH=none
TEST=build scarlet with POWER_SEQUENCING_VERSION == 2 &&
CHIP == stm32
Change-Id: I314b21a909324a7d4666569525d9daddd300abdb
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/572338
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch moves the code which can be shared with other data
verification schemes (e.g. RWSIG) under common/vboot. It also
adds unit tests for it.
BUG=b:38462249
BRANCH=none
TEST=make run-vboot. Verify verification succeeds on Fizz.
Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/563463
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This change is for Scarlet rev1.
BUG=b:62640322
BRANCH=none
TEST=
1) build Scarlet with 'CHIPSET_POWER_SEQ_VERSION == 2' successfully
2) build Kevin (CHIPSET_POWER_SEQ_VERSION == 0),
and verify Kevin still boots
Change-Id: I084a7b51fb1fdd8b6d50aa06189f34054162fc9a
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/568224
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564798
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch adds vboot for EC by EC (vboot EC) for x86 systems.
When ec is transitioning s5->s3, it checks the power supply is
enough to boot AP or not. If not, it runs other checks and may
finally validate and jump to a RW image.
BUG=b:38462249
BRANCH=none
TEST=Boot Fizz on barrel jack and type-c charger.
Change-Id: I5988b0595976370c5303c45541702ae89d86fc97
Reviewed-on: https://chromium-review.googlesource.com/518254
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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We need to refactor power/rk3399.c to make it more flexible
to support different power sequences for upcoming follower boards.
BUG=b:62640322
BRANCH=none
TEST=manaully test on scarlet and kevin:
S0->S3->S0 and S0->S3->S5->G3->S5->S3->S0 work.
Change-Id: I70cdcbaba046bfab4fe832eca58f30524e99e6de
Reviewed-on: https://chromium-review.googlesource.com/540783
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Remove big and pit boards along with several now-obsolete CONFIGs /
source files.
BUG=chromium:735109
TEST=`make buildall -j`
BRANCH=None
CQ-DEPEND=CL:544681
Change-Id: Ieb784bd36157fd1f6240cd19de6e6d12191a8097
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/540667
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Until HOOK_INIT has completed, do not allow any tasks other than HOOKS
or IDLE to be scheduled. Programmers often make the assumption that
a HOOK_INIT function is guaranteed to be run before task code that depends
on it, so let's make it so.
BUG=chromium:649398
BRANCH=None
TEST=Manual on kevin, compare boot without patch:
...
[0.004 power state 0 = G3, in 0x0008] <-- from chipset task
RTC: 0x00000000 (0.00 s)
[0.004 power state 4 = G3->S5, in 0x0008]
RTC: 0x00000000 (0.00 s)
[0.005 clear MKBP fifo]
[0.006 clear MKBP fifo]
[0.006 KB init state: ... <-- from keyscan task
[0.012 SW 0x05]
[0.155 hash start 0x00020000 0x00019a38]
[0.158 HOOK_INIT DONE!]
... to boot with patch:
...
RTC: 0x58cc614c (1489789260.00 s)
[0.004 clear MKBP fifo]
[0.005 clear MKBP fifo]
[0.010 SW 0x05]
[0.155 hash start 0x00020000 0x000198e0]
[0.157 HOOK_INIT DONE!]
...
Also, verify kevin boots to OS and is generally functional through
sysjump and basic tasks, and verify elm (stm32f0 / cortex-m0) boots.
Change-Id: If56fab05ce9b9650feb93c5cfc2d084aa281e622
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456628
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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On PMIC reset, VCC power rail goes down thus resulting in loss of
panic data. Thus, provide a chance to the chip to backup panic data if
available.
BUG=b:62076222
BRANCH=None
TEST=make -j buildall
1. > crash divzero
> panic
=== PROCESS EXCEPTION: 06 ====== xPSR: ffffffff ===
r0 : r1 : r2 : r3 :
r4 :00000001 r5 :00000000 r6 :00000000 r7 :00000000
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12: sp :00000000 lr : pc :
Divide by 0
mmfs = 2000000, shcsr = 0, hfsr = 0, dfsr = 0
2. > crash assert
> panic
=== PROCESS EXCEPTION: 00 ====== xPSR: ffffffff ===
r0 : r1 : r2 : r3 :
r4 :dead6663 r5 :000000a4 r6 :00000000 r7 :00000000
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12: sp :00000000 lr : pc :
mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0
3. > crash watchdog
> panic
=== PROCESS EXCEPTION: 3c ====== xPSR: ffffffff ===
r0 : r1 : r2 : r3 :
r4 :dead6664 r5 :0000000a r6 :00000000 r7 :00000000
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12: sp :00000000 lr : pc :
mmfs = 0, shcsr = 0, hfsr = 0, dfsr = 0
4. > crash unaligned
> panic
=== PROCESS EXCEPTION: 06 ====== xPSR: ffffffff ===
r0 : r1 : r2 : r3 :
r4 :200c0d9e r5 :00000000 r6 :00000000 r7 :00000000
r8 :00000000 r9 :00000000 r10:00000000 r11:00000000
r12: sp :00000000 lr : pc :
Unaligned
mmfs = 1000000, shcsr = 0, hfsr = 0, dfsr = 0
Change-Id: Ife5c9bbc12dcf6c4922f18b7530b21a3b87e65b3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/530138
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Merge PP900_USB_EN, PP900_PLL_EN, and PP900_PMU_EN.
Add a new config flag to enable different power-on sequences
on one SOC.
BUG=chrome-os-partner:62207, b:62307687
BRANCH=gru
TEST=build kevin/gru/scarlet
Change-Id: Iec3082384aa321636c59169b2bc55f773463f3d0
Reviewed-on: https://chromium-review.googlesource.com/434158
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/524979
Commit-Ready: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
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Some hardware has an issue where the reset flags are lost on power cycle
because the EC backup ram loses power. This causes the flag to not power
on the AP (ap-off) to be lost.
In order to pass FAFT it is required that boards support this flag, so
this commit adds a workaround where the skylake chipset code will call into
the board to ask if it has working reset flags and if not it will skip the
PMIC reset if the "ap-off" flag has been set.
The "ap-off" flag is purely for testing, it is not possible for users to
do this without having access to the EC console. (which is currently not
possible at all with CCD unless you can also build a debug cr50 image)
BUG=b:38187362,b:35585876
BRANCH=none
TEST=manual testing on Eve: execute 'reboot ap-off' and ensure that the
AP does not power on. Also ensure that 'dut-control power_state:rec' works
as expected and does not power off at the recovery screen due to a power
button press.
Change-Id: If11e17179e9173509b9a6ae1ef0d94a50ba181d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514503
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This was causing cpu to give lower performance.
Hard throttling is being handled in chipset_throttle_cpu.
BUG=None
TEST=Improved CPU benchmark
Change-Id: I0bff47ec0ce60f31fa1f30fdea94d45dfe05aa38
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://chromium-review.googlesource.com/508569
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
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Fizz has two power sources: barrel jack and type-c port. It
selects a power source at boot and does not dynamicall switch
to the other ports after that.
Fizz initializes all power suppliers of all ports to zero then
initialize the source supplier (barrel jack or type-c port).
When both sources are provided, it prefers a barrel jack. This
detection is done by reading the voltage on PPVAR_PWR_IN.
If barrel jack is detected as a sink, type-c port works as a
source only. If type-c port is detected as a sink, type-c
port works as a sink only.
Fizz does not have a battery. So, battery module is removed.
BUG=b:37573548,b:37316498
BRANCH=none
TEST=Boot on both type-c & barrel jack.
Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/499547
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power_button_x86.c and switch.c assume there is a lid switch. This
patch separate them so that a board with power button but with no
lid can be configured properly.
This patch also moves backlight control to the board directory
so that only the boards with a backlight turn it on/off when power
state changes.
BUG=none
BRANCH=none
TEST=boot fizz. make buildall.
Change-Id: If4070cdc4b1221fae68b35ec3497335d81f192fd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/489602
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The wake mask programming for S0ix is done in
EC. This patch adds handling for the tablet switch
events in the S0ix flows.
BRANCH=none
BUG=b:37223093
TEST=attach or detach base and check if event is generated
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Change-Id: Ibd53e85d5a3a1b776e519b70860404684c9ab0fb
Reviewed-on: https://chromium-review.googlesource.com/486462
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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