| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The debounce timer might be too slow to actually update the state of
debounced_power_pressed by the time we do power_button_is_pressed in the S3->S5
state transition. Solution is to move the power_button_wait_for_release function
here and make sure there are no deferreds active.
BUG=chrome-os-partner:35948
TEST=During dev mode screen, press power button, note the device stays off
TEST=Print debounced_power_pressed in power_button_is_pressed(void), note it's
not 0 when power button is actually pressed
BRANCH=veyron
Change-Id: I8258e9e5524bd65d6ea9c77ea5649304d2195bf0
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/244590
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is to add llama board support:
- new files in board/llama folder, including battery.c and led.c
- new file power/mediatek.c, which is mostly based on power/tegra.c
- modified flash_ec for llama board
- disable tests for llama board.
BRANCH=none
BUG=none
TEST=make BOARD=llama
Change-Id: Ie1ae068c1a402f08e1449668b1be8f31105bb804
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/243510
Reviewed-by: Rong Chang <rongchang@chromium.org>
Tested-by: lok.ben ben.mtk <ben.lok.mtk@gmail.com>
Commit-Queue: lok.ben ben.mtk <ben.lok.mtk@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Alex did the reset workaround in power_on function.
<https://chromium-review.googlesource.com/#/c/214360/>
Now, the new version RK808 has fixed this issue, so we needn't this
workaround.
BUG=chrome-os-partner:35976
BRANCH=veyron
TEST=The BUCK1_ON_VSEL register default value is 0x18, and coreboot and
kernel will change this register to other value, but never set 0x18 to
it. So we can read this register in coreboot and print out to console to
check whether the RK808 reset to default after cold reboot. With this
patch, the value always reset to 0x18. I have test on jerry, mighty,
speedy.
TEST=Use "i2cset -f -y 0 0x1b 0x21 0x0f"
Power up system: it should power back up
TEST=Use "i2cset -f -y 0 0x1b 0x21 0x0f"
Press refresh-power: system should reboot
TEST=Use "i2cset -f -y 0 0x1b 0x2a 0x00"
Shut down and power back up.
Use "i2cget -f -y 0 0x1b 0x2a". Confirm back to 0xff.
TEST=Use "i2cset -f -y 0 0x1b 0x2a 0x00"
Press refresh-power: system should reboot
Use "i2cget -f -y 0 0x1b 0x2a". Confirm back to 0xff.
Change-Id: Icfdd3a7eeadce2c597bf286b36bea0aa58cfe4c4
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/243202
Reviewed-by: Douglas Anderson <dianders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If we don't do this, some code later on (like the S3 hook) might check the
POWER_GOOD too early, note that it's on and move to the wrong state:
[8.457344 power button not released in time]
[8.457541 long-press button, shutdown]
// power_off() happens:
[8.459853 power shutdown complete]
[8.593443 power state 7 = S0->S3, in 0x0001]
[8.593653 power state 2 = S3, in 0x0001]
// power_get_signals check happens here ^^^, but POWER_GOOD did not have enough
// time to fall and cause the power_update_signals interrupt
[8.593863 power state 6 = S3->S0, in 0x0001]
[8.594132 power state 3 = S0, in 0x0000]
// system is actually off here
BUG=chrome-os-partner:34816
TEST=Hold Power+Refresh, release after about 10 seconds, the ec should not
have an assertion error and reboot
BRANCH=veyron
Change-Id: Ic7a06a5d255f2b8d056b0b454fc32a4c05c998b4
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/242620
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 5f954620fa3d36e8e1a88bf7d3963dc7996ec445)
Reviewed-on: https://chromium-review.googlesource.com/242711
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If we sysjump while the AP is running, the AP_RUN sleep mask should be
preserved. Otherwise, the EC goes into low power idle while the AP is
still up.
BRANCH=Ryu
BUG=chrome-os-partner:34230
TEST=Without this change, bit 0 becomes 0 after a sysjump. With this, it
doesn't.
Change-Id: I55cecff3275402f7974c6078a9c203bafce2a2f9
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/238918
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
if power good is lost and the power button still press, we need cancel the long
press timer, otherwise EC will crash.
BUG=chrome-os-partner:34816
TEST=press power button during coreboot, and it can shutdown normally
BRANCH=None
Change-Id: Ia27c83137451abacce9d544741bbbe5787983215
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/237294
Reviewed-by: Jiazi Yang <Tomato_Yang@asus.com>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Eddie Cai <eddie.cai8848@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With this change we can use power event to configure sensors
and trigger motion detection in suspend.
BUG=chrome-os-partner:31071
BRANCH=ToT
TEST=Check power states. Check power up messages and commands are
present at the console.
Message at boot:
[0.007142 hash start 0x00010000 0x000096dd]
[0.007293 Inits done]
[0.007506 power state 2 = S3, in 0x0000]
[0.007765 power state 3 = S0, in 0x0000]
[0.007908 event set 0x00002000]
[0.008021 hostcmd init 0x2000]
[0.146870 hash done
f87d7824b439db923d270df016af5aabec51b73505b7c4faa6e40c16b12dd392]
Change-Id: I9c56fe5203506462f0820bbc8a5fe4528f6805ac
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226881
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Added hibernate wakeup pin(EC_WAKE) that covers both AC_PRESENT and LID_OPEN. It pulses a
rising edge when either of them have a rising edge.
The power button was also inverted to handle hibernation better, now it's low
except when pressed it temporarly goes high.
BRANCH=None
BUG=chrome-os-partner:33269 chrome-os-partner:32782
TEST=make BOARD=jerry
Try hibernating, all wakeup sources should work, it shouldn't stay hibernated.
All signals(AC, lid, power button) should work equally well as in pinky.
Change-Id: I894135bdfd5600919296f7510dc9cd1acd567ddc
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/228763
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Modules that are enabled are listed below:
- Power Sequencing
- Keyboard Scan and Protocol
- LPC to support Keyboard
- Power Button Task
ec.spi.bin has to be generated manualy using
pack_ec.py
BUG=None
BRANCH=None
TEST=Tested on Stargo-Proto board
Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226303
Reviewed-by: Vic Yang <victoryang@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add macro for default hibernate delay, and set to 7 days on samus.
Also, adds CONFIG_ option for hibernating early if low on battery.
For samus, setting early hibernate at 1 day when battery < 10%.
BUG=chrome-os-partner:33088
BRANCH=samus
TEST=make buildall
Added ccprintf("Target shutdown: %.6ld\n", target_time); to print
out target shutdown time after setting it. Verifed the following
on samus
1) If CONFIG_HIBERNATE_DELAY_SEC is left at default 3600 (samus
board.h does not overwrite it), then target time is 3600s.
2) If CONFIG_HIBERNATE_DELAY_SEC is defined in samus/board.h, then
target time equals that value.
3) If CONFIG_HIBERNATE_DELAY_SEC is defined as 1 week and
CONFIG_HIBERNATE_BATT_PCT is defined to 10% and
CONFIG_HIBERNATE_BATT_SEC is 1 day, then when battery is between 8-10%
target time is 1 day and if battery is at 11%, target time is 1 week.
Change-Id: Ief155ad6c327775fa348d3458fc47ee9dd8569c3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is the first step to fix a leak when powering up the system.
Some stuff should wait till after the rails are up.
The SPI timeout was removed because there's a simpler way to determine this:
SPI is only ready when the AP goes from S3->S0
BUG=chrome-os-partner:32824
BRANCH=None
TEST=Pinky powers on
Change-Id: Ia4281f54f7735d4efe2bc3e8ba1e462fccc51fd0
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222632
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
EC need to enable 5v_drv when power on AP, disable it when power off AP.
BUG=None
TEST=USB host works well
BRANCH=None
Change-Id: Ie18679a5a2d3c676daf0af4da599fa010d98161d
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/220162
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The 'power' console command is entirely redundant:
- 'power on' can be replaced by 'powerbtn'.
- 'power off' can be replaced by 'apshutdown'.
- 'power' can be replaced by 'powerinfo'.
Let's remove this command to save flash space.
BUG=chrome-os-partner:32203
TEST=Build Ryu.
BRANCH=None
Change-Id: Ib33804c1748dd44bbb89277fed938b50f0f946c4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219491
Reviewed-by: Alec Berg <alecaberg@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
'powerindebug' is only used when there is a problem with power
sequencing. 'taskready' is rarely used and the same info can be
retrieved by 'taskinfo'.
Put both behind config flags and disable 'taskready' by default. Also
disable 'powerindebug' for Ryu.
BUG=chrome-os-partner:32203
TEST=Build Ryu and check flash space used.
BRANCH=None
Change-Id: I753a1f5411d6e840a80aba03afc94f9640d381a8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/219490
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
| |
BUG=None
TEST=None, no code changes
BRANCH=None
Change-Id: Ie5675938c918d0f79779bf46557aff1074f49512
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217882
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
EC needs to ensure EC_INT & SPI_CS are in input state or output low, Before AP on.
Otherwise it will cause leakage to AP, and power_on timing is incorrect.
BUG=None
TEST=power_on timing is correct.
BRANCH=None
Change-Id: I2dc9c35b4782e4f5c138b31944af21d8248215cd
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/217691
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The PWRON signal is actually a pulse that's only supposed to happen at the S0->S5
transition. We can release it when we see POWER_ON.
BUG=None
TEST=Power on and power off normally. "halt" makes the system go to S5 instead
of rebooting.
BRANCH=None
Change-Id: I14f1cc83c8a4a89226574cf605823d247ce9508a
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/217690
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
There was a way to brick the PMIC by programming its registers with a bad
configuration, this could prevent the AP from powering up properly (thus not
being able to unbrick it). The PMIC retains register state through S5 (presumably
due to RTC business) and they do not get reset at bootup unless the OTP reset is
asserted.
The OTP reset actually has to be asserted in a special(rather long as well)
sequence.
A bug was discovered while making this change(crosbug.com/p/31635): usleep does
not work for long delays. Since I needed at least 300ms on one of the delays I
used a workaround with a loop.
I also cleaned up some old tegra stuff and renamed things to be more semantic.
BUG=None
BRANCH=None
TEST=From the AP set a PMIC register from the default value of 0x7d to 0xfd:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
Check what the default state is, mine was 0x7d
user@ap~$ i2cset -f -y 0 0x1b 0x24 0xfd #or change 0xfd to something!=default
Cold reboot the dut("apreset" or "power on\npower off" will work) then check if
the PMIC registers got reset:
user@ap~$ modprobe i2c-dev
user@ap~$ i2cget -f -y 0 0x1b 0x24
0x7d(or whatever your default state was) #good
0xfd #bad, did not reset properly
Using "user@ap~$ i2cset -f -y 0 0x1b 0x24 0x00" instead will prove the bricking
of the PMIC/AP.
Change-Id: Iad96781ffde085befe6dea20edd255ca3e7e1357
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214360
Reviewed-by: Doug Anderson <dianders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
A cancel is needed when power button is release before timeout
BUG=None
TEST=When in S3/S0, hold the power button for 8 seconds; the system should shutdown.
And release button before that, It's normal.
BRANCH=None
Change-Id: I1baf3a80d7b6349d2e10eb1f7ea9795ee73fb487
Signed-off-by: zyw <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/214750
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Alexandru Stan <amstan@chromium.org>
Tested-by: Alexandru Stan <amstan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Hibernate is not supported on STM32F0. Disable system hibernate so that
the system doesn't auto-reboot after an hour in G3. This also benefits
us in terms of firmware size.
BUG=chrome-os-partner:31665
TEST=Boot on Ryu. Check 'hibdelay' and 'hibernate' commands are absent.
TEST=Boot Ryu from G3.
TEST=Change default hibernation delay to 1 second. Put system in G3.
Check it does not reboot.
BRANCH=None
Change-Id: Ia01d2d74bc5c22c01e29e5877bd4bd38ee7dddc8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/214834
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
There's no point in having these delays, they're not applicable to Veyron.
BUG=None
TEST=Everything should work the same.
BRANCH=None
Change-Id: Icc2aebae1a497dd4f46579c23e36750feca6d67a
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213248
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
I readded the code that armed the power_off_deadline. The force power-off should
be controlled fully from the EC now.
BUG=None
TEST=When in S3/S0, hold the power button for 8 seconds; the system should shutdown.
BRANCH=None
Change-Id: I848ce6757e497c15296aa4eae9c05133950b4e45
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213249
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Seems that we were driving GPIO_PMIC_PWRON_H backwards. The only reason it
worked before is because of a stale feature from tegra which pretty much kept it
always disabled(enabled in our case due to _L).
Also removed old power signals and renamed signals so they're more semantic and
respect convention(no _H).
BUG=None
TEST=AP should boot as normal, gpioget will show both PMIC_*PWR* pins 0 when
system off and 1 when system is on. The system will also use 8mA less now
(no more current leak into the PMIC).
BRANCH=None
Change-Id: I81b7596cb39a5c2b45d53e05478396b91040cacf
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/213246
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When long power press is canceled, we need to cancel the current running
timer. Otherwise, if the power button is pressed again before the
current running timer expires, the next deadline won't be set. This
causes the chipset task to wake up too early and miss the subsequent
long power press shutdown.
BUG=chrome-os-partner:31372
TEST=On Ryu, long press following a short press shuts down the system.
BRANCH=None
Change-Id: I9855b146d430e5babda727fcb429c516ca91e48e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/212560
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change EC_INT pin to high-Z to reduce power draw in S5, and reset it
to output High in S5S3.
BUG=None
TEST=Leakage did not happen, other functions also work correctly.
BRANCH=None
Change-Id: Id77bb9f34f25336cd097344be349f5aa43a75b52
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/210545
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some PMIC chip (e.g. TPS65913) doesn't support the 8-second long key
press power-off. For this, we have to check the state of the power
button in firmware, and do not assert PMIC_PWRON during the shutdown
sequence to prevent the AP from restarting.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=with the next CL, on Ryu, do a long power button key press, and see
the AP powering off and not restarting.
Change-Id: I03f703b4ff6d86edea150dfa32f60d30f1ddffd9
Reviewed-on: https://chromium-review.googlesource.com/207381
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Pulled down line so it's not so erratic.
Fixes the issue where the EC doesn't know what state the AP is in.
BUG=None
TEST=EC should report S0 correctly(not S3 all the time). `power on` and
`power off` will also work correctly(instead of doing absolutelly nothing).
BRANCH=None
Change-Id: I69bd17b39d2bd8f7f0456c4babc4ad9f8f34c8bd
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/209668
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
It is now the proper name.
BUG=None
TEST=None, only name changed. EC should work as expected still.
BRANCH=None
Change-Id: Ia63db6fa0dc41750ebf31423c9870f8a463bf392
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/209814
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch is base on new hardware board, veyron has not some stuff,
such as power led, charge en
BUG=None
TEST=Read log with servo board, it has reponse when type some commends
BRANCH=None
Change-Id: I45502fd1278f69db5e46fc9ab1deaee02fc8708f
Signed-off-by: zyw <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/209231
Reviewed-by: Alexandru Stan <amstan@google.com>
Commit-Queue: Alexandru Stan <amstan@google.com>
Tested-by: Alexandru Stan <amstan@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use the power signal list abstraction everywhere to access the SUSPEND_L
GPIO.
This is preparatory work for Ryu, so we can change the suspend GPIO name
and active level.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: I1ad3471600f1207986a6be9d8c3c627ab73796ac
Reviewed-on: https://chromium-review.googlesource.com/207151
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The SPI init should run before we power up AP. Otherwise, the AP
would try to talk to EC before the EC SPI is ready. This could fail
the first SPI transcation.
BUG=chrome-os-partner:30083
BRANCH=Tot,nyan
TEST=build and run on Nyan only.
Change-Id: Ie40ba5210c49446c94c01d697aa66568730de83f
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206181
Reviewed-by: Vic Yang <victoryang@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When this option is configured, two changes take place.
First, the AP doesn't power on by default when the EC reboots. To boot it,
you can run the "powerbtn" command, or poke the power button manually, or
any of the normal things.
Second, we watch for power-related signal changes (anything that's connected
to the power_signal_interrupt() function) and keep track of them as they
happen. After a second with no further changes, we print the time and value
of each change. For example:
[19.939212 Port 80: 0x29]
[19.967971 HC 0x23]
[19.976236 Port 80: 0x3a]
[19.995700 HC 0x87]
[20.567884 Port 80: 0x73]
11 signal changes:
19.638241 +0.000000 PCH_SLP_SUS_L => 1
19.654378 +0.016137 PCH_SLP_S5_L => 1
19.654457 +0.000079 PCH_SLP_A_L => 1
19.654535 +0.000078 PCH_SLP_S3_L => 1
19.654587 +0.000052 PCH_SLP_S4_L => 1
19.659630 +0.005043 PGOOD_1_5V_DDR => 1
19.663199 +0.003569 PGOOD_1_5V_PCH => 1
19.664751 +0.001552 PGOOD_1_8VS => 1
19.668735 +0.003984 PGOOD_VCCP => 1
19.671883 +0.003148 PGOOD_VCCSA => 1
19.868406 +0.196523 PGOOD_CPU_CORE => 1
[21.908551 Port 80: 0xf0]
[21.908855 HC 0x48]
BUG=none
BRANCH=ToT
TEST=manual
Build with CONFIG_BRINGUP, notice those two changes.
Change-Id: I55fd2021a0eae7dbfd1aaf5d93971f65bf2367b9
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/202574
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Our code base contains a lot of debug messages in this pattern:
CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n")
The strings are taking up spaces in the EC binaries, so let's refactor
this by adding cprints() and ccprints().
cprints() is just like cprintf(), except that it adds the brackets
and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...)
This saves us hundreds of bytes in EC binaries.
BUG=chromium:374575
TEST=Build and check flash size
BRANCH=None
Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200490
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The auto_power_on is set 1 unexpectedly while EC jumps. This has a
side effect that would turn on the AP unexpectedly after "power off".
See comment 43 of issue 28249
BUG=chrome-os-partner:28249
BRANCH=tot,nyan
TEST=on nyan:
> reboot
> sysinfo
// If EC is in RO, "sysjump RW"
> power off
// The AP keeps off.
Change-Id: I3c06e99383c06af7cd6c17dd65040e20f06d8e73
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198941
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a follow-up for CL 197990 and 197991. See issue tracker for
more details.
BUG=chrome-os-partner:28289
BRANCH=tot,nyan
TEST=Copy from https://chromium-review.googlesource.com/#/c/197990
Going battery shipmode and plug-in AC, See booting and expect EC log:
"[... battery initialized]"
Disconnect battery, and plug-in and see booting and expect EC log:
"[... battery not responding]"
Change-Id: Ic218414c21057a971b478ec60e406f1eb69dd379
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198412
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
FAFT expects the "AP running" shows first, then "XPSHOLD seen".
BUG=chrome-os-partner:28316
BRANCH=tot,nyan
TEST=build only
Change-Id: Ic3e9d68b7727d62d3ccc2c037e7547f0276c2eae
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198766
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If we follow the TEST steps below, the power state machine in AP
and EC were out of sync -- due to the un-clear bit and wrong
initial power state.
BUG=chrome-os-partner:24835
BRANCH=tot,nyan
TEST=on big.
> reboot
> power off // De-assert XPSHOLD
> reboot ap-off
> sysinfo // This reset flags does NOT contain "ap-off".
> power on
% ectool reboot_ec RW // The following message is NOT observed.
// "system is on, but RESET_FLAG_AP_OFF is on".
> power // This should show the AP is "on".
// ensure everything still works.
> reboot ap-off // AP keeps off.
> reboot // AP is on.
Change-Id: I51afed7201d16ebcd889ad12a7af90026591cc2d
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198587
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The power_request variable is not clear in apshutdown case. Thus,
the AP comes up again by the "power up" request. Clear this variable
only when apshutdown command to avoid affecting the regular power
states.
BUG=chrome-os-partner:28621
BRANCH=tot,nyan
TEST=see below
> reboot // or other methods to turn on the AP.
> power on
> apshutdown
// The AP should remain off.
Change-Id: Icfc8a50db95aba656168f5b10dabd9443d75338d
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198770
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some battery uses clock stretching feature, and this could disturb
PMU communication before battery going stable.
AP does not know and will attempt PMU setting, and could get fail
For various battery indicates usually 1s for stable
(even if it is much less in real world 200ms~700ms)
Let's checking 'battery is ready' when first pump-up power.
BUG=chrome-os-partner:28289
TEST=Going battery shipmode and plug-in AC, See booting and EC log
Disconnect battery, and plug-in and see booting and EC log
Change-Id: I9b62266132d5322366265afe03adbe0db1f9ae75
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/197991
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
See issue tracker for details.
BUG=chrome-os-partner:28518
BRANCH=tot,nyan
TEST=on big
% reboot ap-off
% powerbtn
[6.100943 power on 4]
Was power on 1 before fix.
% reboot
[0.098134 power on 2]
Was power on 1 before fix.
Change-Id: I7b2fd95234d16467edca041b1c12d63ca4b5112b
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198070
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
XPSHOLD is not always removed after chipset_force_shutdown(). This is
different to the GAIA design. So, check the RESET_FLAG_AP_OFF flag
again while check_for_power_on_event().
BUG=chrome-os-partner:28371
BRANCH=tot,nyan
TEST=verify on big.
re-flash ec: power on 2, AP is up.
AP is on, reboot@EC: power on 1, AP is up.
AP is off, reboot@EC: power on 2, AP is up.
AP is on, reboot ap-off@EC: AP keeps off (see FLAG_AP_OFF flag)
AP is off, reboot ap-off@EC: AP keeps off (see FLAG_AP_OFF flag)
reboot ap-off@EC, then 'powerbtn': AP is off at boot, then power on 4
reboot@EC: power on 2, AP is up.
re-plug AC (remove battery): power on 2
re-plug battery (without AC): power on 2 (but my battery is dead)
power off (S5), power on: power off 4, power on 5
power off (G3), power on: power off 4, power on 5
lid close / power off (S5)/ lid open: power on 3
lid close / power off (G3)/ lid open: power on 3
press power button and release: nothing happens after 15s. AP keeps in S5.
button off (S5)/ on: power off 3, power on 4
button off (G3)/ on: power off 3, power on 4
power off (S5)/ button on: power off 4, power on 4
power off (G3)/ button on: power off 4, power on 4
button off (S5)/ power on: power off 3, power on 5
button off (G3)/ power on: power off 3, power on 4
button off (S5)/ lid open: power off 3, power on 3
button off (G3)/ lid open: power off 3, power on 3
is off, long press button (60s): power on 4, too long, shutdown, stay off
is on, long press button (60s): power off 3, stay off
AP is on, apreset cold: entered to S5, power off 3, power on 5
AP is on, apreset warm: power state is not changed, but reboots to BIOS
Change-Id: I9ccd13ab4b5f38be1ad8d6c9a04724b56bc5b166
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197604
Reviewed-by: David Hendricks <dhendrix@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In some cases, the system will boot to S0 from the point of view of
the EC, but PLTRST# will never deassert. Work around this by waiting
50 ms for PLTRST# to deassert. If it doesn't, force the chipset all
the way down by deasserting RSMRST#, then pulse the power button to
turn it back on.
Also add a powerfail debug command to simulate this failure event, so
that the recovery process can be tested.
Add API to the LPC module to get the state of PLTRST#, and to the
power button state machine to force it released when we shut down the
chipset and and force another power button pulse as we reset the
chipset.
BUG=chrome-os-partner:28422
BRANCH=baytrail
TEST=1. Boot system. Should boot normally. Shut system down.
2. powerfail
3. Boot system. On the EC console, should see the system come up,
go back down through G3S5, then come back up. From the user's
point of view, it just boots.
1. Boot system. Should boot normally. (That is, powerfail is not sticky)
Change-Id: Ia57f196606f79b9f2fce7d9cd109ab932c3571aa
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197523
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This would move all tegra boards to charger v2.
Also removed the unnecessary charge_keep_power_off(), which was
designed for USB power port and doesn't apply to Tegra platform.
BUG=none
BRANCH=nyan,big,blaze
TEST=build and run on nyan.
Change-Id: I9517a8885726ad6dce5a2865402da4b9551e009f
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/194384
Commit-Queue: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Devin Lu <Devin.Lu@quantatw.com>
Tested-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Refactored keyboard scan enable/disable flag such that it is a mask of
potential disable sources. When all disable sources are off, scanning is
enabled, otherwise scanning is disabled. This fixes a recently introduced
bug in which enabling/disabling keyboard scanning due to lid angle in S3
was interfering with enabling/disabling keyboard scanning due to power
button. This also allows for easy expansion for future causes for disabling
keyboard scanning.
BUG=chrome-os-partner:27851
BRANCH=rambi
TEST=Manual tests with a glimmer. Used the ksstate console command to
check state of keyboard scanning under all permutations of power button
pressed/unpressed, lid switch open/closed, and lid angle in tablet position
vs. laptop positon.
Change-Id: Ied4c5ebb94510b1078cd81d71373c0f1bd0d6678
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/194287
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We had decreased this from 100 ms to 5 ms, but apparently we need at
least 10 ms. Use 15 ms to give us some margin.
BUG=chrome-os-partner:25264
BRANCH=rambi
TEST=boot system
Change-Id: I4d96aeb1040a042bac46fa8701a073d3355bfd2a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190485
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This works around an issue where LCDVCC falls too slowly. The impact
is to slow shutdown by 7 ms, which isn't noticeable to the user.
BUG=chrome-os-partner:26561
BRANCH=rambi
TEST=shut down rambi; still shuts down, and ~7 ms more time is spent
in S0->S3 state.
before:
[429.933010 power state 3 = S0, in 0x043f]
[429.933240 power state 7 = S0->S3, in 0x043f]
[429.933614 power state 2 = S3, in 0x042b]
[429.934013 power state 8 = S3->S5, in 0x0428]
after:
[20.355975 power state 3 = S0, in 0x003f]
[20.356194 power state 7 = S0->S3, in 0x003f]
[20.363957 power state 2 = S3, in 0x002c]
[20.364179 power state 8 = S3->S5, in 0x002c]
[20.364877 power state 1 = S5, in 0x0008]
Change-Id: Ie843bdcf740f3dbc1b866a0356cea2a8b42d4194
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189092
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We don't have available GPIO pin for power button as the hibernate
(stand-by) wake-up source. Also, we don't want to do board change.
So, put the EC in a decent infinite loop to pretend the hibernate mode
and wait for particular wake-up event. This should be fine because
the AP is already down before EC hibernates.
BUG=chrome-os-partner:25435
BRANCH=Nyan
TEST=see comment #6 of issue for detailed test steps.
Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186061
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Previously, the AP could only set the current wireless power state.
It couldn't determine what the EC would do in S3, nor could it get the
current wireless power state. Extend the wireless command to do so,
and add an EC console command to aid in debugging.
BUG=chrome-os-partner:25655
BRANCH=rambi
TEST=manual; expected numbers are from EC 'wireless' command
AP off -> 0x0, 0x9
AP on -> 0xd 0x9
AP suspended -> 0x9 0x9
AP on -> 0xd 0x9
ectool wireless 0x1 -> 0x1 0x9
ectool wireless 0xd -> 0xd 0x9
ectool wireless 0 0 0 0 -> 0xd 0x9 (and prints 0xd 0x9 to root shell)
ectool wireless 5 -1 -1 0 -> 0x5 0x9
AP suspended -> 0x1 0x9 (doesn't turn on 0x8, just turns off 0x4)
AP on -> 0xd 0x9
ectool wireless 0 0 0 -1 -> 0xd 0x0
AP suspended -> 0x0 0x0
AP on -> 0xd 0x9
Change-Id: I8ead2d4a4423b51ec4f638bf94c62de98726b25c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187273
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Nyan uses common/charge_state instead. So, fix the dependence.
Since snow/spring/pit are using common/pmu_tps65090_charger, keep them.
BUG=None
BRANCH=Nyan
TEST=build and works fine on Nyan 3.2
Change-Id: I985f7980578ac22602b1fbffa51edf039078bc05
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since we have only mini-PCIe devices, and no PCIe devices, we don't need a 100 ms delay.
BUG=chrome-os-partner:25264
BRANCH=rambi
TEST=boot system; AP boots normally
Change-Id: I3dd537154d70b8379ebc36cb71474420cba43d7d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|