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* oak: ensure PMIC power button is released after SYSJUMP.Ben Lok2015-10-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | There is a race condition between SYSJUMP and function release_pmic_pwron_deferred(). Process of EC SW Sync will delay the execution time of release_pmic_pwron_deferred(). PMIC will shutdown the power, if PMIC power button can not be released within 8 seconds (depends on PMIC spec). In order to ensure PMIC power button will be released in time, just release it after SYSJUMP. BUG=chrome-os-partner:46392 BUG=chrome-os-partner:46656 BRANCH=none TEST=make buildall -j; Enable EC SW sync and normal mode in coreboot, Kernel should bootup successfully. Change-Id: I45d4aa0f0d4280e68282ea11ccfda05201f88aae Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/307220 Reviewed-by: Rong Chang <rongchang@chromium.org>
* skylake: Move USB enable gpio control to board hooksDuncan Laurie2015-10-121-7/+0
| | | | | | | | | | | | | | | Some boards may not have a USB2_ENABLE GPIO so we need each board to do the USB power enable/disable in a board hook. BUG=chrome-os-partner:46289 BRANCH=none TEST=make -j buildall Change-Id: I830cbaf41c118b2f74e23fa946a4187f6293a7d5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/304397 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_commands: Add "hibdelay" as an EC host command.Aseda Aboagye2015-09-251-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | Currently, the only way to prevent a system from hibernating is via the EC console command "hibdelay". This commit adds the host command equivalent so that it can be set elsewhere. The host command takes the amount of time in seconds to delay hibernation by and responds with the current time in the G3 power state, the time remaining before hibernation should be invoked, and the current setting of the hibernation delay. BUG=chrome-os-partner:45608 BUG=chrome-os-partner:44831 BRANCH=None TEST=Build and flash on samus. Issue the host command from EC console. Verify that the hibernation delay was updated by checking with the hibdelay command. Change-Id: I34725516507995c3c0337d5d64736d21a472866c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/302197 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* oak: updates GPIO setting for rev4Ben Lok2015-09-231-1/+5
| | | | | | | | | | | | | | | | | | | | | Modify the GPIO seeting according to the Oak rev4 schematic. BRANCH=none BUG=none TEST=manual Confirm all reversion of oak can be built pass: make -j EXTRA_CFLAGS=-DBOARD_REV=4 BOARD=oak make -j BOARD=oak clean make -j EXTRA_CFLAGS=-DBOARD_REV=3 BOARD=oak make -j BOARD=oak clean make -j EXTRA_CFLAGS=-DBOARD_REV=2 BOARD=oak make -j BOARD=oak clean make -j EXTRA_CFLAGS=-DBOARD_REV=1 BOARD=oak Change-Id: Ib1051f29df9d1919f0ae3ecaf55dc0997ea29c3e Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/300728 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: revise the cold reset timing.Ben Lok2015-09-181-9/+19
| | | | | | | | | | | | | | | | | | | | | | | since we add debounce time (50 ms) for SUSPEND & POWER GOOD signal after oak rev3 (commit e58a913b). It will causes the chipset_reset function failure, because PMIC_COLD_RESET_L_HOLD_TIME is short. PMIC_COLD_RESET_L_HOLD_TIME should be greater than 100 ms [SUSPEND_DEBOUNCE_TIME (50 ms) + POWER_DEBOUNCE_TIME (50 ms)]. So, revise PMIC_COLD_RESET_L_HOLD_TIME to 120ms. And, using hook to avoid blocking the EC console when executing "apreset" EC console command. BRANCH=none BUG=chrome-os-partner:44955 TEST=manual Run EC console command, after AP enter S0: > apreset AP should be reset normally. Change-Id: I04e31aef8be3092ad39b5f1b1c2b75b78b4d1d7b Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/299625 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: power: set 8s for long power key press to force shutdownYH Huang2015-09-181-5/+5
| | | | | | | | | | | | | | | | | Since the firmware_ECPowerButton testcase holds down power button about 10s to shut down without powerd, we set DELAY_FORCE_SHUTDOWN about 8s to make sure the powerbutton is pressed long enough to force shutdown. BRANCH=none BUG=chrome-os-partner:43412 TEST=manual run "firmware_ECPowerButton" testcase on rev3. Change-Id: Ib41cdecfa0342236d618e6fdffcb64bf7f51b557 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/296884 Reviewed-by: Rong Chang <rongchang@chromium.org>
* Kunimitsu: Enable support for limiting the inrush currentVijay Hiremath2015-09-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | Enable the support for limiting the inrush current by routing the PCH_SLP_SUS through EC gpio PMIC_SLP_SUS which allows the DUT to boot on charger without the battery / dead battery. This is applicable to Kunimitsu FAB4 only. Enabling the Glados patch for Kunimitsu FAB4. Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13 Reviewed-on: https://chromium-review.googlesource.com/287378 BUG=chrome-os-partner:44706 TEST=FAB4 prototype boots to UI without battery / dead battery. BRANCH=none Change-Id: Ie81cdf3c59fc02d6d59dd06ca321705ca06e7b88 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/296521 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: enable MBKP events for PD eventsBen Lok2015-08-312-4/+4
| | | | | | | | | | | | | | | | | | | (refer to CL:273620) enable the MKBP event feature to send host event and wire up the PD specific events. But, CONFIG_MKBP_EVENT conflicts with CONFIG_KEYBOARD_PROTOCOL_MKBP, due to the GPIO name of EC interrupt pin. Align the GPIO naming of EC interrupt pin to EC_INT_L. BRANCH=none BUG=chrome-os-partner:44643 TEST=On Oak rev3, plug/unplug USB devices and add kernel trace to see the PD events happening. Change-Id: I10de9c6611583bb6165bdc1848e542d4b8bba954 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/296012 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* Fixed a failure of power button press while entering G3 state.Kaiyen Chang2015-08-311-6/+43
| | | | | | | | | | | | | | | | | | | | | | If the power button is pressed while S5 inactivity timer is about to expire, EC need to give CPU a little time to start up before changing the state from S5 to G3 (the hard off state); otherwise the system will not start up. This issue can be reproduced on Rambi. BUG=chrome-os-partner:42728, chrome-os-partner:42811 BRANCH=None TEST=Implement an ec command to simulate power button press while S5 inactivity timer is about to expire, and then make sure that the patch did solve the issue. Change-Id: I022e8e14fd41447898760a4d57a4702e2c00a0d5 Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/290280 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296436 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* skylake: allow power button power ons in S5 after apshutdownAaron Durbin2015-08-311-3/+3
| | | | | | | | | | | | | | | | | | | On skylake the apshutdown command holds the power button asserted until the power state machine decides to deassert the power button. Previously this check was taking place in G3 state. As such when the board waited in S5 for 10 secs one couldn't re-power on the system. To alleviate that move the logic for power button deassertion into the S5 state. BUG=chrome-os-partner:44532 BRANCH=None TEST=Used apshutdown. When device got to S5 power noted another powerb command would bring the system back up instead of waiting to enter G3 power state. Change-Id: I9989b27bd48819d7c3e5efd071b0327c38fe91e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295198 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* glados: Disable keyboard + trackpad in tablet modeShawn Nematbakhsh2015-08-241-3/+1
| | | | | | | | | | | | | | | | The internal keyboard and trackpad must be disabled in tablet mode to prevent unwanted input. BUG=chrome-os-partner:44305,chrome-os-partner:40849 TEST=Manual on Glados. Boot system with lid open, verify that keyboard is functional and ENABLE_TRACKPAD is high. Swing lid to tablet mode, verify that keyboard is not functional and ENABLE_TRACKPAD is low. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9f250ae82963c8b497de991b6cce52c86841d08a Reviewed-on: https://chromium-review.googlesource.com/295206 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Skylake: Add low power Pseudo G3 supportVijay Hiremath2015-08-211-3/+19
| | | | | | | | | | | | | BUG=none TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu. With only battery after 1 hour, device enters to Pseudo G3 and the V3p3A is off. With AC connected, device is in G3. BRANCH=none Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/292976 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake: power sequencing updateAaron Durbin2015-08-191-36/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number issues with the current skylake power sequencing. First, SLP_SUS_L was not being honored from the chipset when a deep S5 or S3 was requested. Additionally the BATLOW_L signal was being used to block the chipset from waking which caused a race in waking from deep S5 that required an additional pulse of the PCH_WAKE_L signal instead of the chipset seeing the power button event. Another issue is that POWER_S5 state was being completely bypassed so any global resets that brought down SLP_S4_L caused the state machine to enter into G3 state. The code was changed to remove BATLOW_L usage, PCH_WAKE_L in the POWER_G3S5 state, and SLP_SUS_L is honored in the non POWER_S5G3 and POWER_G3 state. That allows SLP_SUS_L pass-thru to work on glaods. Lastly the code was reorganized to accomodate the above change without sprinkling them throughout the state transitions. BUG=chrome-os-partner:44081 BUG=chrome-os-partner:44082 BUG=chrome-os-partner:43475 BRANCH=None TEST=Built and booted glados. Deep S3 and S5 wakes work. Fresh flash plus a global reset doesn't bring the system down to G3. Change-Id: Id1d7af1b6a733a9db5aad584950da8ab5898ea83 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293844 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: Wake from Deep S5 after battery low is deassertedstabilize-7374.BDuncan Laurie2015-08-171-7/+16
| | | | | | | | | | | | | | | The system will not wake from Deep S5 if BATLOW# is asserted, so wait for that to deassert, then pulse the wake pin and wait for SLP_SUS_L to deassert. BUG=chrome-os-partner:43545,chrome-os-partner:44079 BRANCH=none TEST=verified on P2 board Change-Id: I3b36159b574d418c9b79c478d0a41f753474fa6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293595 Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: Switch to V2 boardShawn Nematbakhsh2015-08-141-3/+7
| | | | | | | | | | | | | Switch to V2 glados as the default, and remove support for V1. BUG=chrome-os-partner:43075 TEST=`make buildall -j` BRANCH=None Change-Id: I58f33225177d259916e8877084c2c431922e7bc5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* strago: Power state transition in case of apshutdownKumar, Gomathi2015-08-111-0/+4
| | | | | | | | | | | | | | | | | | | In case of 'apshutdown', during transition to S5 state, GPIO_PCH_SLP_S4_L signal was not getting deasserted but required rail went away (GPIO_PCH_SYS_PWROK). So it was going on a loop S5 -> S3 and S3 -> S5. In strago GPIO_PCH_SYS_PWROK is the PMIC_EN GPIO and hence conditinally setting it based on CONFIG_PMIC BUG=none TEST=apshutdown on strago BRANCH=none Change-Id: I9c581a3dfcb9cc84a22b41505e7df496d72d5f4c Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com> Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-on: https://chromium-review.googlesource.com/292024 Reviewed-by: Shawn N <shawnn@chromium.org>
* mediatek: Fix llama buildShawn Nematbakhsh2015-08-061-15/+1
| | | | | | | | | | | | | | The llama AP_RESET GPIO differs in polarity from oak. BUG=chromium:517250 TEST=`make buildall -j` BRANCH=None Change-Id: Id06bf39e758b528d154936a3e8561704fdf4cce9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290950 Commit-Queue: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* oak: increase the PMIC power key press time to 5 seconds.Ben Lok2015-08-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | There are 3 methods to power on the system: 1) Pulling PWRKEY low (User presses PWRKEY) 2) Setting BBWAKEUP high 3) Valid charger plug-in We should ensure that BBWAKEUP should be high when release PWRKEY. Due to the RTC driver of coreboot will move to ramstage, and the setup timing of BBWAKEUP will be postpone. In order to ensure PMIC keeping the power until coreboot pull BBWAKEUP up, it needs to increase the PMIC power key press time to avoid PMIC turn the power off. This change is related to: https://chromium-review.googlesource.com/#/c/257389/ BRANCH=none BUG=none TEST=manual Update coreboot with above patch, press power key and system should power on normally. Change-Id: I7fabc49e0b3956885cb83a0b40c31c60080d0cbc Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/290538 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: revise warm reset control for rev3Ben Lok2015-08-051-9/+21
| | | | | | | | | | | | | | | | | | | | | | The AP warm reset pin is changed from rev3 of oak board. PB3 is stuffed before rev3 and connected to PMIC RESET pin to reset the AP. For rev3, the AP reset mechanism is changed: PC3 connects to PMIC SYSRSTB, pull PC3 to low, to reset AP. BRANCH=none BUG=none TEST=manual 1. define CONFIG_BOARD_OAK_REV_2 in board.h make -j BOARD=oak 2. define CONFIG_BOARD_OAK_REV_3 in board.h make -j BOARD=oak both cases should be built successfully and run "apreset" command. AP should be reset normally. Change-Id: I979e93acf755509f8cb7a12dd77eb7c9e7a98ccc Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/289476 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: enable EC sleep in S3Ben Lok2015-08-051-3/+8
| | | | | | | | | | | | | | | In S3, the EC isn't expecting AP host commands, so it's safe to enable sleep BRANCH=none BUG=none TEST=Check sleep mask in S0 and S3. Also check sleep mask after sysjump with AP on and with AP off. Change-Id: I9dcfe996e8e92e6703d71bbe966cd2447c6b14fe Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/290002 Reviewed-by: Rong Chang <rongchang@chromium.org>
* oak: power: Set 10s for long power key press to force shutdownYH Huang2015-08-031-5/+5
| | | | | | | | | | | | | | | | | In order to pass the test case "firmware_ECPowerButton", I change the value of DELAY_FORCE_SHUTDOWN from 11s to 10s. The test case holds down power button about 10s to shut down without powerd. BRANCH=none BUG=none TEST=manual run "firmware_ECPowerButton" test case. Change-Id: I3da93769f1cb52b04c447df9a7795d3c28ab2bf0 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/282153 Reviewed-by: Rong Chang <rongchang@chromium.org>
* tasks: Remove most task_start_called() calls.Aseda Aboagye2015-08-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Now that HOOK_INIT hooks are called from a task switching context, most calls to task_start_called() should no longer be needed. This commit removes them. BRANCH=None BUG=chrome-os-partner:27226 TEST=make -j buildall tests TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard, lid, and tap-for-battery all functional. TEST=Flash EC image onto samus_pd and verify charging still works. TEST=Flash EC image onto ryu(P3) and verify that EC boot. TEST=Added ASSERT(task_start_called()) to the places where I removed task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC inserted and verified that no ASSERT's were hit upon boot. Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/285635 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* skylake: Inhibit AP power-on until charge current limit is setShawn Nematbakhsh2015-08-011-0/+24
| | | | | | | | | | | | | | | | | | Inhibit AP power-on through the BATLOW pin, even if the system is unprotected, until our charger and current limit are initialized. Note that this feature is only functional on glados v2 since other skylake boards do not have BATLOW connected. BUG=chrome-os-partner:41258 TEST=Manual on glados v1 with rework. Remove battery and attach Zinger. Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP boots. Remove all power and attach battery, verify that EC powers on and AP boots. Also verify compilation on glados v2. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13 Reviewed-on: https://chromium-review.googlesource.com/287378
* oak: power: change power state while losting POWER_GOOD signalYH Huang2015-08-011-16/+76
| | | | | | | | | | | | | | | | | Check IN_POWER_GOOD signal in S0 and go to S3 if IN_POWER_GOOD is lost. Finally it will go to S5(G3). Check suspend and power good signal after POWER_DEBOUNCE_TIME to avoid transient state. BRANCH=none BUG=none TEST=manual Test power related commands such as "shutdown -P now" or "apshutdown". Change-Id: Ia06fc7d8334c0dfbb0263474f57e4dca7313d331 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/282680 Reviewed-by: Rong Chang <rongchang@chromium.org>
* mec1322: Power state transition in case of apshutdownKyoung Kim2015-07-281-0/+21
| | | | | | | | | | | | | | | | In case of 'apshutdown', SOC loses power immediately while EC is waiting for SOC's PMC_SUSPWRDNACK signal forever. BUG=chrome-os-partner:43038 TEST=Cyan BRANCH=none Change-Id: I34321d00a89011e90222ea5916a42e9a51d4f4b0 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/288203 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* glados: V2 Board ChangesShawn Nematbakhsh2015-07-241-0/+11
| | | | | | | | | | | | | | | Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2, which is not defined by default in order to support existing boards. BUG=chrome-os-partner:42933 TEST=Verify that Glados v1 board continues to boot AP. Verify compilation on GLADOS_BOARD_V2. BRANCH=None Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287291 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Skylake: Add G3 sleep mode supportVijay Hiremath2015-07-211-0/+3
| | | | | | | | | | | | | BUG=none TEST=Enabled the config and tested on Kunimitsu. Enter "shutdown -h now" form the Kernel console. Device goes to Sleep mode in G3 and charger LED turns off. BRANCH=none Change-Id: I962018dcfac2998ee0a11784adeceb09931b930d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/286781 Reviewed-by: Shawn N <shawnn@chromium.org>
* Braswell: Add support for PMICKyoung Kim2015-07-151-21/+12
| | | | | | | | | | | | | | | | Added support for PMIC in Braswell power sequencing code to support the PMIC enabled Braswell devices. BUG=none TEST=Tested S3, S5, G3 & PG3 on BCRD2. BRANCH=none Change-Id: I247ef9506d0e8065c761bfb00b9141ec8ff5ada8 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283579 Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: Disable power rails and components when appropriateShawn Nematbakhsh2015-07-151-1/+9
| | | | | | | | | | | | | | | | | - Disable USB, wireless and audio power rail when powering down from S3 - Disable sensor power rail and display backlight when powering down from S0 BUG=chrome-os-partner:42104 TEST=Manual on Glados. Boot AP, verify that display backlight and USB are functional. BRANCH=None Change-Id: I2879f57db555753b280e785df3d2cc967c152f21 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/285545 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Strago/Cyan: Change USB power pin name to generic one.li feng2015-07-141-6/+0
| | | | | | | | | | | | | | | | Removed USB enable/disable as it will be handled by HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled. BUG=none TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value changed when state switch between S3 and S5. BRANCH=none Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867 Signed-off-by: li feng <li1.feng@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283593 Reviewed-by: Shawn N <shawnn@chromium.org>
* Braswell: Added SOC G3 / Pseudo G3 supportKevin K Wong2015-07-142-4/+39
| | | | | | | | | | | | | | | | BUG=none TEST=Tested on DVT 1.1, verified V3p3A is off in Pseudo G3 BRANCH=none Change-Id: Id73b42d9f2e49239e82fad7931bbcc63e36a2c0b Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283602 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* oak: set a debounce time for suspend signalBen Lok2015-06-301-1/+13
| | | | | | | | | | | | | | | | | The suspend signal from SoC of oak should be kept at least 50ms. Add a debounce time for suspend singal detection, to avoid transient state during SoC boot up. BUG=chrome-os-partner:42023 BRANCH=none TEST=plug PD power adaptor to type-c port C1, The keyboard should be worked (Ensure EC communication is oaky) Change-Id: I4a6bb4e8ba9d417fe2a3045846d38b2129516d78 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/282471 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* tegra: enable EC sleep in S3Vic Yang2015-06-261-1/+2
| | | | | | | | | | | | | | | | | In S3, the EC isn't expecting AP host commands, so it's safe to enable sleep. BRANCH=Ryu BUG=chrome-os-partner:36918 TEST=Check sleep mask in S0 and S3. Also check sleep mask after sysjump with AP on and with AP off. Change-Id: I67f0634631f62ee571e18d2870cd4a6926d4e090 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/251750 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* oak: power: add the console command "power on/off"YH Huang2015-06-251-1/+60
| | | | | | | | | | | | | | Add the console command "power on/off" for AP power on/off. BRANCH=none BUG=none TEST=manual enter "power on/off" in the ec console to turn AP power on/off. Change-Id: I16d2af72bc1bf045e7672acd9471dff0a672aff5 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/280957 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* power: ryu: ignore lid open eventsVincent Palatin2015-06-251-1/+2
| | | | | | | | | | | | | | | | | | Do not start the AP on lid open events, in order to avoid spurious startup due to magnet magic. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:41601 TEST=Play with 2 Ryu EVT2 stacked one on top of the other. Change-Id: I530d54f61d0674caddf20d1b17268c971f639f2f Reviewed-on: https://chromium-review.googlesource.com/281667 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* oak: power off ap if reboot ap-offYH Huang2015-06-231-22/+28
| | | | | | | | | | | | | | | When ec gets the console command "reboot ap-off", turn off ap. BRANCH=none BUG=none TEST=manual Enter "reboot ap-off" in ec console and then ap is off. Change-Id: Iba2c3743ae37ee9ceaadba58752d2129fb00d3a8 Signed-off-by: YH Huang <yh.huang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/277976 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Rong Chang <rongchang@chromium.org>
* power: skylake: Delay 10ms before deasserting PCH_RSMRST_Lstabilize-7199.BShawn Nematbakhsh2015-06-201-1/+17
| | | | | | | | | | | | | | | According to spec, RSMRST shouldn't be deasserted until 10ms after power signals become active. BUG=chrome-os-partner:41556 TEST=Manual on Glados. Verify that AP boots to S0 on power-on, goes to G3 on apshutdown, and back to S0 on powerbtn. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0acc897fff7c18ad83fc87734569ec7639ae5cf4 Reviewed-on: https://chromium-review.googlesource.com/280571 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* skylake: Properly handle apshutdown when AP is already shutdownShawn Nematbakhsh2015-06-131-2/+4
| | | | | | | | | | | | | | | | If the AP is already shutdown, apshutdown would previously power the AP up with a power press. Fix this by making sure we're not already in G3 before triggering the power press. BUG=chrome-os-partner:40677 TEST=Run 'apshutdown' on glados while in G3, verify that AP does not power up. BRANCH=None Change-Id: I8b898b034dcf40f0acef4fb6098af0aebba566c6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277400 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Remove obsolete board-specific codeRandall Spangler2015-06-102-348/+0
| | | | | | | | | | | | | | | | | Now that we've removed boards from ToT, also delete board-specific code used only by the removed boards. There are still more things to remove (unused charging chips, LED drivers, COMx support). More CLs coming. BUG=chromium:493866 BRANCH=none TEST=make buildall -j Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/276524 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* skylake: Use a simulated power button press to force-shutdown the APShawn Nematbakhsh2015-06-041-2/+13
| | | | | | | | | | | | | | | | Holding the power button is currently the best known way to bring the AP back to a state where it is shutdown and not powered. BUG=chrome-os-partner:40826, chrome-os-partner:40677 TEST=Run `apshutdown` on glados, verify that power state machine transitions to G3 after several seconds. Run `powerbtn`, verify that state machine transitions back to S0. BRANCH=None Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275060 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* glados: Initialize PMIC V12 / V0.85A supplyShawn Nematbakhsh2015-05-291-0/+3
| | | | | | | | | | | | | | This change is necessary to ensure power-up of edge-case Skylake parts. BUG=chrome-os-partner:40677 TEST=Manual on Glados. Boot system to S0, run "i2cxfer r 4 0x60 0x38", verify that 0x7a is read. BRANCH=None Change-Id: Id9e62731aaa75fb2357a05d898ba2d4d28f87d9e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274114 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* power: skylake: Wait for PCH_SLP_SUS_L deassertion when leaving G3Shawn Nematbakhsh2015-05-291-1/+1
| | | | | | | | | | | | | | | | PCH_SLP_SUS_L can take up to 29ms to be deasserted after power-on or RTC reset. BUG=chrome-os-partner:40677 BRANCH=None TEST=Manual on glados. Power board, verify that state machine transitions to S0. Run "reboot" on EC console, verify that state machine again transitions to S0. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3f6e89eee1190a3fe84fdc7d939c05dfe5b94953 Reviewed-on: https://chromium-review.googlesource.com/274077 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* power/skylake: Always enable PP*_EN signals for bring-upShawn Nematbakhsh2015-05-281-12/+0
| | | | | | | | | | | | | | Always enable these signals to help debug power sequencing. We'll need to revert this change later. BUG=chrome-os-partner:40677 BRANCH=none TEST=sequence to S0 on glados and stay there Change-Id: Ia845532fe7aed71bcb42b4ca6a9bfa20aa9e3e00 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273900 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* power: skylake: Always mirror rsmrst input to outputShawn Nematbakhsh2015-05-281-6/+2
| | | | | | | | | | | | | | This change will help us to debug power sequencing and will likely need to be reverted later. BUG=chrome-os-partner:40677 BRANCH=none TEST=sequence to S0 on glados and stay there Change-Id: I85d1f0f97a3c93cf26c766a749feb23f9cf4ac62 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273680 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* oak: add initial support for oak board rev1Rong Chang2015-05-271-44/+52
| | | | | | | | | | | | | | | Add initial support for Oak rev1 board. This is just the EC and includes battery charging but does not include USB PD. BUG=none BRANCH=none TEST=load on oak board and get console Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Alec Berg <alecaberg@chromium.org> Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777 Reviewed-on: https://chromium-review.googlesource.com/261678
* Skylake: Fix for "apreset cold" EC console commandVijay Hiremath2015-05-181-1/+2
| | | | | | | | | | | | | | Debounce time for the GPIO SYS_RESET_L is 16ms hence increased the time delay between SYS_RESET_L pin toggling to 20ms. BUG=chrome-os-partner:40246 TEST=Tested "apreset cold" EC console command on Kunimitsu BRANCH=none Change-Id: If17229ce485de708b550ec84939e2696e451cb0c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/270776 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* glados: Initial mainboard commitstabilize-7060.BShawn Nematbakhsh2015-05-121-1/+1
| | | | | | | | | | | BUG=chrome-os-partner:39510 TEST=Compile Only BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If470b00fec56db0884dbd4c9974140951fc214fd Reviewed-on: https://chromium-review.googlesource.com/268780 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* power: skylake: Add support for skylake power sequencingShawn Nematbakhsh2015-05-122-2/+248
| | | | | | | | | | | | | | Add power sequencing for Skylake, following the IMVP8 / ROP PMIC design for SKL-U / SKL-Y. BUG=chrome-os-partner:39510 TEST=Compile only BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ibf6a0e4415544b6b4b2cf28c167106ce4bfdc54e Reviewed-on: https://chromium-review.googlesource.com/269460 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* power: Move EC_CMD_GSV_PAUSE_IN_S5 handler to common codeShawn Nematbakhsh2015-05-074-104/+60
| | | | | | | | | | | | | | | | The same code exists in four (soon to be five!) different power sequencing drivers, so move it up to common. BUG=None TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console, verify that system again goes to G3 on shutdown. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c Reviewed-on: https://chromium-review.googlesource.com/269566 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Braswell: Turn on/off the USB power while S5->S3/S3->S5.Hsu Henry2015-05-051-0/+7
| | | | | | | | | | | | | | The USB power is off in S5 with previous ChromeBook. The braswell platfrom should be the same as before. BUG=chrome-os-partner:39507 BRANCH=cyan TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console. Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/267451 Reviewed-by: Shawn N <shawnn@chromium.org>
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