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* power/mt8183: Remove use of GPIO_PP1800_S0_EN.Yilun Lin2018-06-201-2/+0
| | | | | | | | | | | | | TEST=make BOARD=kukui BUG=None BRANCH=None Change-Id: I09b8efb1215abfc53904a8ceb8273d88ef9fbbb1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1105804 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Remove Kahlee boardMartin Roth2018-06-151-8/+0
| | | | | | | | | | | | | The Kahlee/CDX03 board is no longer used. BUG=b:77693343 TEST=None BRANCH=None Change-Id: I2e0495dc1895d03b54cd6d1b9e13e1b84efb5bad Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1091394 Reviewed-by: Jett Rink <jettrink@chromium.org>
* host_event: Handle SCI/SMI masks correctly when using S0ixFurquan Shaikh2018-06-151-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When host is using S0ix, BIOS is not involved during suspend or resume paths. Thus, until now, SCI and SMI masks were preserved across S0ix suspend/resume cycles. However, it was identified in b:78497503 that if SCI is generated after host enters S0ix, then it results in EC eSPI controller waiting for host controller to respond to the SCI virtual wire event. This prevents the EC from entering low power idle mode. In order to fix the above issue, this change ensures that SCI and SMI masks are cleared when host expresses its interest to enter S0ix. Since these masks are not re-programmed by the host on resume, EC maintains backup copies of both the masks. On resume from S0ix, backup copies are used to restore the masks for SCI and SMI. This change applies to both eSPI and LPC systems since SCI/SMI should not be generated (physical or virtual) when host is in S0ix. This implementation follows the design proposed in: https://docs.google.com/document/d/1J2VYeVXV-KZnIHvtDyOrcH4AXJipsSX6m8oZIDSdtv8/edit?usp=sharing BUG=b:78497503 BRANCH=None TEST=Verified following: 1. SCI and SMI masks are programmed correctly on boot-up. 2. SCI and SMI masks are set to 0 when host enters S0ix. 3. SCI and SMI masks are restored correctly on S0ix resume. Change-Id: Iaa3981e6545d2d3cff51649642f6926f0d4ec31f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1099968 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power/mt8183: Power sequencing logic for MT8183Nicolas Boichat2018-06-142-0/+329
| | | | | | | | | | | | | | | | | | | | | | | | | MT8183 uses a power sequencing inspired from RK3399, with fewer signals. We only have 1 signal from PMIC (PMIC_PWR_GOOD), active in S0/S3, and 1 signal from AP (AP_IN_S3_L), active in S3/S5. One particularity of this design is that we need to reboot the EC to RO on every single cold boot/reboot. For the forced transition to S5, we assert the WATCHDOG signal to PMIC to shut it down, which should usually work, if the PMIC was configured properly by AP. If not, we also assert power+home key (PMIC_EN_ODL) until the PMIC shuts down for good. BRANCH=none BUG=b:109850749 TEST=make BOARD=kukui -j Change-Id: Ibcde8b937d7f4cecb0f470b9a7e0809fc24efae6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1092402 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Add CONFIG_* option for PROCHOT polarity.Aseda Aboagye2018-06-083-0/+17
| | | | | | | | | | | | | | | | | | | The common x86 chipset code assumed that CPU_PROCHOT was active high, however on some boards it's actually active low. This commit simply adds a CONFIG_* option, CONFIG_CPU_PROCHOT_IS_ACTIVE_LOW, and inverts the places where the signal is used. BUG=b:109882953 BRANCH=poppy TEST=Enable on nocturne; flash, verify that CPU_PROCHOT is not asserted by default. Change-Id: I6d871e4979b79333cf4897d77c995eadbb34fd43 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1092150 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Fizz: add CONFIG_BOARD_HAS_RTC_RESETRyan Zhang2018-06-071-0/+5
| | | | | | | | | | | | | | | | | | | | | This patch resets the RTC of the SoC when the system doesn't leave S5. If it fails 5 times, the system will go back to and stay in G3. BUG=b:79323716 BRANCH=fizz TEST=Boot Fizz differently: 1. AC plug-in 2. Power button press 3. reboot EC command 4. servo reset button 5. Recovery mode Change-Id: I728c99c342fb888600599acbe25f72a478ccf948 Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020583 Reviewed-on: https://chromium-review.googlesource.com/1089035 Reviewed-by: Duncan Laurie <dlaurie@google.com>
* power: Rename rockchip to rk3288Nicolas Boichat2018-06-072-1/+1
| | | | | | | | | | | | | Get rid of a TODO. BRANCH=none BUG=b:35569119 TEST=make buildall -j Change-Id: Ia918c90519220a348f8c65b6b6f14b6d3129a63a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090523 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* power: Rename mediatek to mt817xNicolas Boichat2018-06-072-2/+2
| | | | | | | | | | | BRANCH=none BUG=b:109850749 TEST=make buildall -j Change-Id: I69538a210f9b2198614720537faa3ee75bc0600e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090522 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stoney: Rename GPIO_PCH_RCIN_L to GPIO_SYS_RESET_LJonathan Brandmeyer2018-06-051-2/+2
| | | | | | | | | | | | | | Pin rename only; no functional changes. See also b/72426192 for earlier functional changes. BUG=b:77301519 TEST=make -j buildall BRANCH=none Change-Id: I18e71118e584a5b36ba001bac24951929d2c93ff Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1087207 Reviewed-by: Edward Hill <ecgh@chromium.org>
* stoney: strip unused forcing_coldreset path.Jonathan Brandmeyer2018-06-041-12/+2
| | | | | | | | | | | | | | This is just a dead code elimination; no functional changes. See also b/72426192 for functional changes. BUG=b:77301519 TEST=power cycle on grunt EVT BRANCH=none Change-Id: Id9f60d14eb2a7df9013f779b05a54638ad62971f Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1083317 Reviewed-by: Edward Hill <ecgh@chromium.org>
* APL/GLK: Clean up UART buffer before shutdownVijay Hiremath2018-05-231-0/+8
| | | | | | | | | | | | | | | | | | | | UART buffer gets overwritten by other tasks if it is not explicitly flushed before printing it on the console by same task. Hence, clean up the UART buffer so that all the debug messages are printed on the UART console before doing shutdown. BUG=b:79950369 BRANCH=none TEST=Manually tested on BIP, observed that UART logs are not lost on the terminal when apshutdown is issued. Change-Id: I420e9de9e2e71913ee3168267a6f3a2728b2690b Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1064977 Commit-Ready: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* espi: rename remaining eSPI optionsJett Rink2018-05-232-6/+6
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cheza: Check power enough and enable PP5000 when power-on APWai-Hong Tam2018-05-221-0/+51
| | | | | | | | | | | | | | | | | | | | | | | Remove the previous hack of force increasing the adapter current. The PP5000 rail is now turned on/off during power-on/off AP. Add a check to ensure it has enough power to enable the 5V rail and boot AP. If the battery is in low level or unplugged and the charger adapter doesn't supply enough power, don't boot AP and transition back to S5. The check may wait a while for PD negoiation. BRANCH=none BUG=b:79353631 TEST=On battery plugged and unplugged cases, checked the device can source VBUS to USB port-0 and port-1. TEST=Unplug battery and use a low-power adapter, can't boot up AP. See the "Not enough power to boot" message and transition to S5. Change-Id: Ie9b8dff6e10d97dffd554b382595e5e7a70875e6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1050607
* cheza: Support confirmation of power lostTom Wai-Hong Tam2018-05-081-2/+51
| | | | | | | | | | | | | | | | | | | | | | Keep the timestamp of the latest power lost. Add a handler to wake the chipset task to check if power lost stays low for a while (the time between now and the latest power lost is longer than a period). BRANCH=none BUG=b:78455067 TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset sequence and verified AP reset but not a transition S0 -> S5. TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse (see power_off function) to execute PMIC shutdown sequence and verified a power-lost transition S0 -> S5. Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028831 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Enable AP_RST_REQ as a request from AP to reset itselfWai-Hong Tam2018-05-081-1/+27
| | | | | | | | | | | | | | | | | | | | | | | This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising edge interrupts to trigger a hook to call chipset_reset(). As the hook task will be preempted by the chipset task, it adds a flag bypass_power_lost_trigger to avoid triggering to S5 as the chipset state machines sees power lost during the reset. So far the chipset_reset() implementation is to do a cold reset; will be revised to a warm reset after the PMIC registers are reprogrammed. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Ran 'reboot' on AP console which toggles the GPIO. Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1023986 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Make sure switchcap is configured rightAlexandru M Stan2018-05-041-1/+1
| | | | | | | | | | | | | | | | | | Configure switchcap every time we're about to change the signal, just in case it forgot. Feel free to revert this after b/77957956 is fixed. BRANCH=none BUG=b:77957956 TEST="i2cxfer r 0 0xd0 0x2" never shows 0x70, even after a bad brownout (like "gpioset EN_PP5000_A 1" on an unreworked board) Change-Id: I8994cd402ce96d8bf4e436dadfc0e572e7f77a85 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024501 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Add SDM845 power sequence for rev-0 boardWai-Hong Tam2018-05-042-0/+641
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the power sequence for rev-0 board. Confirmed the behavior of reprogramming the PMIC registers to enable the instant reset and shutdown. BRANCH=none BUG=b:74395451 TEST=make buildall -j TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control pwr_button:press sleep:0.2 pwr_button:release Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0 * Console command: power off Result: S0 -> S5 -> G3 * Console command: power on Result: G3 -> S0 * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923 Signed-off-by: Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969702
* power/rk3399: Check aborted suspend for s0s3_usb_wake_power_seqPhilip Chen2018-04-201-1/+5
| | | | | | | | | | | | | BUG=b:78321971 BRANCH=scarlet TEST=build kevin and scarlet Change-Id: I9e0c842cd8f4186147fa8e6d001b1c21ddad7e89 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1022746 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org>
* power/common: Preserve 5v enable across sysjumpJustin TerAvest2018-04-191-0/+25
| | | | | | | | | | | | | | | | | | | | | | The value of pwr_5v_en_req needs to be preserved when the EC performs a sysjump, otherwise any task calling power_5v_enable(tid, 0) will drop the 5v rail for the entire system. I've scheduled this at HOOK_PRIO_FIRST for restoring the value to ensure that no other init hooks read a stale value, but I'm not sure if that's necessary. BUG=b:78275296 BRANCH=none TEST=Booted yorp with power only connected to USB-C port 0 Change-Id: I3a9ed24a5fde02b60163ad2c5e3252759f8c1c5b Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020066 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stoney: Use chipset_pre_init callbackFurquan Shaikh2018-04-191-2/+7
| | | | | | | | | | | | | | | | Similar to intel_x86, move chipset stoney to using chipset_pre_init callback. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I995bbda01ec78ecd28c302f269cf15739913ecd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018738 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-191-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Get rid of CHIPSET_PRE_INIT hookFurquan Shaikh2018-04-191-3/+0
| | | | | | | | | | | | | | | | | Now that all boards are moved to using chipset_pre_init_callback, get rid of hook notification for CHIPSET_PRE_INIT from x86 power state machine. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I244848b3c80e8ccd34b3c99c8aa2dee3030e0e53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018736 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chipset: Add callback for chipset pre-initializationFurquan Shaikh2018-04-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a callback for chipset_pre_init_callback which is made by x86 common power state machine when in G3S5 state. Until now, there was a hook CHIPSET_PRE_INIT_CALLBACK that was notified by chipset task when in G3S5 state. However, there are at least following reasons why this should be a callback and not a hook notification: 1. The initialization that is done as part of pre-init could be essential for the power state machine to make progress. Though the chipset task goes to sleep waiting for power signals after the hook notification, pre-initialization can all be done as part of a callback since it is mostly board-specific code that is doing work to initialize PMIC. 2. Typically, boards use I2C transactions to setup PMIC on getting chipset pre-init notification. However, since i2c transfers are not encouraged in hook task, they have to be deferred anyways. 3. Since the initialization is being done as part of hook task, use of any constructs e.g. pwr_5v_en_req which allows multiple consumers to enable/disable power rails will use task id for hook task. Instead it is better to provide correct information about the task by letting chipset task perform this request. Thus, this change adds a callback chipset_pre_init_callback in G3S5 state for x86 power state machine. This callback is guarded by CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK. The hook notification is left as is for now until all x86 boards are moved over to using the newly added callback. BUG=b:78259506 BRANCH=None TEST=None Change-Id: I2e1d73e5308759fef41680ae715ef71268b61780 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018733 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Code cleanup: Remove cold reset logicVijay Hiremath2018-04-036-85/+37
| | | | | | | | | | | | | | | | | | | | | Majority of the chipsets do not have a dedicated GPIO to trigger AP cold reset. Current code either ignores cold reset or does a warm reset instead or have a work around to put AP in S5 and then bring back to S0. In order to avoid the confusion, removed the cold reset logic and only apreset is used hence forth. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually tested on GLKRVP, apreset EC command can reset AP. Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/991052 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stoney: Rename PGOOD GPIOsEdward Hill2018-03-261-14/+14
| | | | | | | | | | | | | | | Rename stoney power signals for clarity: SPOK -> S5_PGOOD VGATE -> S0_PGOOD BUG=none BRANCH=none TEST=power grunt on and off Change-Id: Iee8307138600c10868981a22971beace2de1ca91 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978952 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-254-50/+31
| | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* apollolake: Remove AP cold reset logicVijay Hiremath2018-03-251-29/+8
| | | | | | | | | | | | | | | | | | | | | In APL & GLK, cold reset code does a AP force shutdown (with board specific AP shutdown code) by power sequencing the SOC all the way to S5 and bring it back to S0. However there is no separate GPIO in APL & GLK for doing AP cold reset hence removed the AP cold reset logic. BUG=b:72426192 BRANCH=none TEST=make buildall -j Manually verified on GLKRVP, apreset cold & warm behave same Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974107 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-2/+2
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power: create CONFIG_CHIPSET_GEMINILAKEJett Rink2018-03-202-3/+4
| | | | | | | | | | | | | | | | | | Geminilake uses the same power sequencing code as Apollolake. Instead of the board specifying the wrong chipset, we will make the correct chipset reuse the existing power code. This also gives us flexibility in the future if GLK needs to vary from ALK in any of shared code. BRANCH=none BUG=b:74020444 TEST=build all Change-Id: Icd00286ac4f0612d1bda56677c4141957480c6bf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969613 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* debugging: Correcting console channel to chipset instead of switchJett Rink2018-03-061-1/+1
| | | | | | | | | | | | BRANCH=none BUG=none TEST=build all Change-Id: I900dbe9f9053310c4cef2d125445fc8aa0fe6b67 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949724 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cleanup: fixing typoJett Rink2018-03-061-1/+1
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I7139fb8e23bd613f2a3ce86057a9210577e74c6c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949723 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* grunt: Disable system power (_A rails) in G3Edward Hill2018-02-121-33/+48
| | | | | | | | | | | | | | | | | | | | | | EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A. These should be off in G3 and on in S5 and higher. VGATE (S0 power) is pulled high in G3 when SPOK (system power, S5) is low because PP5000_A turns off, so add a check for this and only pass through high VGATE when SPOK is also high. Leave kahlee behavior unchanged (power stays on in G3). BUG=b:72744306 BRANCH=none TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3 Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/904729 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* scarlet: shutdown PP900_S0 power rail when S3Lin Huang2018-02-091-2/+2
| | | | | | | | | | | | | | | | | | | we need to shutdown PP900_S0 power rail when S3 to save power consumption, let's do it. BUG=b:62644399 BRANCH=none TEST=run suspend_stress_test, it pass 1000 cycles CQ-DEPEND=CL:890228 Change-Id: I366effe9d2a99cb608069dd5d599171d32a9b4ce Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/841902 Commit-Ready: Brian Norris <briannorris@chromium.org> Tested-by: Derek Basehore <dbasehore@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* Fizz: Execute PMIC reset before vboot_mainDaisuke Nojiri2018-02-081-1/+3
| | | | | | | | | | | | | | | | | | | When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* scarlet: Assert SYS_RST_L in S5Philip Chen2018-01-231-1/+11
| | | | | | | | | | | | | | | | | | | | | To support CR50 deep sleep mode: In up-sequence, SYS_RST_L needs to remain asserted on the transition to S5 and then deasserted on the transition to S0; In down-sequence, SYS_RST_L needs to be asserted on the transition to S5. This only affects Scarlet. BUG=b:35647982 BRANCH=none TEST=minitor SYS_RST_L pin to confirm it is toggled right Change-Id: Ic73d39c531f9d28b2087a23d58613e98ec80dbd2 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/866115 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/rk3399: Change power-off sequence for KD panelPhilip Chen2018-01-161-1/+1
| | | | | | | | | | | | | | | | | We should turn off PP3300_S0 and then PP1800_S0 to meet KD panel spec. PP3300_S0 has to be on in S3_WoUSB, so PP1800_S0 also has to be on - let's move PP1800_S0_EN to s0s3_usb_wake_power_seq. BUG=b:71057948 BRANCH=none TEST='suspend_stress_test' for 10+ cycles without seeing things go wrong Change-Id: Ic44411062b4c9e857b9f8ca6565550ba8bd2f950 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/862254 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* glkrvp: Enable eSPI instead of LPC including eSPI VW based SCI/SMIShamile Khan2018-01-161-0/+4
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=GLKRVP can boot to OS when a coreboot image with eSPI enabled is flashed. Change-Id: Ia534bdbbe517c53ba2e0beafc41b421872f1e33d Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/818196 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* grunt: Fix ENABLE_BACKLIGHT to be active lowEdward Hill2018-01-141-4/+0
| | | | | | | | | | | | | | BUG=b:71806495 BRANCH=none TEST=backlight turns on in S0 Change-Id: Ib9271d6cbe9befdf4ed492a9c2b676452e5f4d9b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865155 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* power: Fix interrupt enable in siglog_deferredEdward Hill2018-01-111-1/+1
| | | | | | | | | | | | | | | | Recent eSPI change (d813935) resulted in siglog_deferred leaving interrupts disabled. BUG=b:71764538 BRANCH=none TEST=apshutdown on grunt, see power signal changes Change-Id: I33e234ad7191af92e2c4ffef700fc5b9356c3c71 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/860571 Commit-Ready: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
* espi: Add API to test if signal is eSPI virtual wireScott Worley2018-01-022-12/+20
| | | | | | | | | | | | | | | | | | | | | | Add espi_signal_is_vw in new file common/espi.c for testing if a signal is an eSPI virtual wire. API used in power common and intel_x86. Fix CONFIG_BRINGUP support for eSPI (off by default). Add espi_vw_get_wire_name returning a pointer to constant string. Chip modules do not need to maintain names of eSPI signals. BRANCH=none BUG= TEST=Build poppy and other eSPI enabled boards. Test power state machine. Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/836818 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* power/rk3399: Fix the power sequence length passed to power_seq_run()Philip Chen2017-12-201-2/+2
| | | | | | | | | BUG=b:63037490 BRANCH=none TEST=build scarlet Change-Id: I80b068a7846037f43e7b385cf8e2ee0b08f42b15 Signed-off-by: Philip Chen <philipchen@google.com>
* cleanup: power/rk3399: Remove unused power sequencePhilip Chen2017-12-201-45/+0
| | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I87c7a6274cbcb355a71987b26e8f092fbdbe8fa0 Signed-off-by: Philip Chen <philipchen@google.com>
* power: cannonlake: SLP_SUS_L deasserted == S5.Aseda Aboagye2017-12-201-0/+6
| | | | | | | | | | | | | | | | When SLP_SUS_L is deasserted, that means the chipset is in S5. BUG=None BRANCH=None TEST=Flash meowth; boot from AC only, verify that when SoC actually boots the power state is reported as S0 instead of G3. Change-Id: Ib9cd76aa9efd6f81df432205b8c1e8c342e32af6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/837485 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* power: cannonlake: Fix power state tracking.Aseda Aboagye2017-12-121-16/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cannonlake power state chipset code would fail to keep an accurate record of the chipset's power state. For example, the EC could claim that the AP was in G3, whereas the SLP_SUS_L signal was deasserted. This commit fixes a few issues with the chipset code. - First, don't have PP3300_DSW_EN enabled by default coming out of reset. The default chipset power state when the EC comes out of reset is G3, therefore we should not enable the PP33000 DSW rail until we decide to leave G3. This is usually triggered by a power button press. - Similarly, when we wish to enter G3, we should turn off the PP3300 DSW rail instead of the noop that was done before. - Lastly, turn on the 5V rail when entering S5 instead of S3 and turn it off when leaving S5 to G3. BUG=b:70184397,b:70244199 BRANCH=None TEST=Flash zoombini; Verify that AP boots to S0 and can shutdown to S5 and the EC tracks it. Verify that after the S5 inactivity timer, we fall to G3. Verify that SLP_SUS_L is asserted and DSWPWROK is low. Verify that we can still perform BC1.2 detection in G3. `reboot ap-off` and verify that the AP does indeed remain off and no port 80 codes are seen. TEST=Verify that 5V is off in G3, but can be turned on if needed. TEST=Verify that 5V is on in S5. TEST=With the exception of BC1.2, repeat the above tests for meowth. Change-Id: I444a8f29969ef6a68a83d1734912d239bad429a5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/813501 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power/rk3399: Poll IN_PGOOD_S0 on up-sequenceShawn Nematbakhsh2017-12-121-4/+23
| | | | | | | | | | | | | | | | | | | | | | Waiting out HOOK_TICK_INTERVAL for a non-interrupt power signal can cause boot delays of up to 500ms, which can lead to dropped host commands and other bad side effects. Poll IN_PGOOD_S0 when sequencing up to reduce the minimum delay to 5ms. BUG=b:70390178 BRANCH=None TEST=Run "reboot" on EC console, check timestamp of S0 transition print: [0.332974 power state 3 = S0, in 0x000f] Compare to pre-patch: [0.692799 power state 3 = S0, in 0x000f] Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4b8891f75d896b1ae47d8f12ed07581f20b6ae7c Reviewed-on: https://chromium-review.googlesource.com/822594 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* grunt: Add delay to PWR_GOODEdward Hill2017-12-112-20/+9
| | | | | | | | | | | | | | | | | | Add delay of 1ms with stable power before asserting PWR_GOOD. CDX03 seems to work ok with and without the delay, but since it is a requirement in the electrical data sheet, better add it. Also removed an unnecessary header while I was here. BUG=b:70350333 BRANCH=none TEST=power CDX03 on and off Change-Id: I9f2f94bfb907ac9e88f350e72286061a97ebfe3d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/816063 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* host_events: Introduce unified host event commandJenny TC2017-12-062-49/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unified Host Event Programming Interface (UHEPI) enables a unified host command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events. Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F) is supported for backward compatibility. But newer version of BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT) The UHEPI also enables the active and lazy wake masks. Active wake mask is the mask that is programmed in the LPC driver (i.e. the mask that is actively used by LPC driver for waking the host during suspended state). It is same as the current wake mask that is set by the smihandler on host just before entering sleep state S3/S5. On the other hand, lazy wake masks are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set the active wake mask depending upon the type of sleep that the host has entered. This allows the host BIOS to perform one-time programming of the wake masks for each supported sleep type and then EC can take care of appropriately setting the active mask when host enters a particular sleep state. BRANCH=none BUG=b:63969337 TEST=make buildall -j. And verfieid following scenario 1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix 2). suspend_stress_test with S3 and S0ix 3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm wake sources (Lid, power buttton and Mode change) 4). Verified "mosys eventlog list" in S5 resume to confirm wake sources (Power Button) 5). Verified above scenarios with combination of Old BIOS + New EC and New BIOS + Old EC(making get_feature_flags1() return 0) Change-Id: Idb82ee87fffb475cd3fa9771bf7a5efda67af616 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/576047 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Commit-Ready: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Auto power-on after battery SOC is above minimum requiredFurquan Shaikh2017-11-281-5/+49
| | | | | | | | | | | | | | | | | | | | | | | | If power-up is inhibited by charger because of battery SOC, then check for the conditions again on BATTERY_SOC_CHANGE. This allows the EC to boot the AP up on connecting AC power and SOC going above the minimum required. BUG=b:65864825 BRANCH=None TEST=Verified following on coral and soraka: 1. Discharge battery to ~0% 2. Connect AC power ==> Power-up is inhibited 3. When battery SOC reaches 1%. AP is not taken out of reset: "[12.974428 Battery 1% / 8h:4 to full] [12.980439 power-up still inhibited]" 4. When battery SOC reaches 2%, AP is taken out of reset: "[9.230148 Battery 2% / 4h:5 to full] [9.236122 Battery SOC ok to boot AP!]" Change-Id: Ifa89f8929987d86c9e02530b663d563dbe25ed85 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753294 Reviewed-by: Shawn N <shawnn@chromium.org>
* cannonlake: Check for hard and soft off in chipset_force_shutdownFurquan Shaikh2017-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | Similar to CL:774298, intention of chipset_force_shutdown is to power off the AP by simulating power button press until it results in power button override and shuts down AP. However, if AP is already in hard or soft off conditions (i.e. G3, S5G3, G3S5 or S5) then AP is already off, and simulating power button press results in charge_prevent_power_on from incorrectly assuming that the power button is pressed by user. Thus, check if the system is in soft or hard off before shutting it down. BUG=b:65864825 BRANCH=None TEST=make -j buildall Change-Id: I4b6d798af4618cbd4179f8700ebb2aa78021207e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/791933 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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