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* qcom: Move the execution of warm reset to CHIPSET contextWai-Hong Tam2022-01-271-11/+28
| | | | | | | | | | | | | | | | | | | | | In CrOS EC, the `apreset` command is executed in the CONSOLE context. But in Zephyr, the command is executed in the lowest priority task context. This low priority task is easily preempted and makes the power signal missing. This miss is wrongly treated as the PMIC not respond correctly and trigger a cold reset sequence: S0 -> S5 -> S0. This CL moves the execution to the CHIPSET task context. It is now independent from the console runtime. BRANCH=None BUG=b:215252361 TEST=Call the `apreset` command, just a warm reset triggered. Change-Id: I2be65db46b453421c2a04d10a75c01dbf16f1f89 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3418118 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* qcom: Rename the POWER_REQ_COLD_RESETWai-Hong Tam2022-01-271-4/+4
| | | | | | | | | | | | | Make the name clearer to reflect the request of the cold reset. BRANCH=None BUG=b:215252361 TEST=Trigger the `apreset` command and have the same behavior. Change-Id: I4dbd241433945449cd41db5cf956312462280cee Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3418117 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* qcom: Refactor the AP warm reset sequenceWai-Hong Tam2022-01-271-9/+26
| | | | | | | | | | | | | | | | | Separate the warm reset sequence to the function warm_reset_seq(). Rename the power-on sequence to the function power_on_seq(). Rename the power-off sequence to the function power_off_seq(). No logical change. BRANCH=None BUG=b:215252361 TEST=Trigger the `apreset` command and have the same behavior. Change-Id: I90a5a547b8b182b9236fed3d73a0a4febc56ee0c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3418116 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* zephyr: Change power_common tests to avoid tasksJeremy Bettis2022-01-121-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Change test_power_exit_hard_off and test_power_reboot_ap_at_g3 to run before ec_app_main, to avoid background tasks. Remove force_power_state from stubs. I plan to remove more code from stubs and replace it with real code from qcom.c, and force_power_state is one of the things that needs to be deleted. BRANCH=None BUG=b:214256453 TEST=zmake testall Change-Id: I022344b1352e0daebf3d12ba623bc78b79f6f2ff Signed-off-by: Jeremy Bettis <jbettis@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3384478 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Aaron Massey <aaronmassey@google.com> Commit-Queue: Aaron Massey <aaronmassey@google.com>
* power: add mt8186 power sequenceTing Shen2022-01-072-0/+411
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT8186 power sequence is a simplified version of 8192/95. EC does not lie between AP and PMIC, so there's no need to forward the signals. Other logics are almost the same. BUG=b:206338930 TEST=Test following items on krabby CL:3233784 * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control 'ec_uart_cmd:powerbtn 8200' Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control 'ec_uart_cmd:powerbtn 200' Result: G3 -> S0 * Console command: apreset Result: S0 -> S5 -> S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=none Cq-Depend: chromium:3366102 Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iebfe77c8f6d127ee4d0685903b67afd215ca6682 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3233783 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* power/icelake: Add SLP_S5 as a watched power signalEvan Green2021-12-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Add SLP_S5_SIGNAL_L as a power signal we start observing and reporting changes on for alderlake. Note that without CONFIG_HOSTCMD_ESPI_VW_SLP_S5, no software actually responds to changes on this line. Additionally, without the above config switched on, SLP_S5_SIGNAL_L defaults to SLP_S4_SIGNAL_L, so we're actually watching VW_SLP_S4 and reporting it as SLP_S5_DEASSERTED. There's nothing technically wrong with this (since nobody takes any action now on the new signal anyway). But to keep things comprehensible I'll add a dependency on the change that flips on VW_SLP_S5 support, where we'll actually start watching, reporting on, and responding to VW_SLP_S5 under its correct power signal name. BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Cq-Depend: chromium:3289944 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I23191e2a422f1813c2a3d72614f2d7503aacde20 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3310528 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* power/alderlake: Add SLP_S5 as a watched power signalEvan Green2021-12-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Add SLP_S5 as a power signal to watch and generate interrupts for when it changes. This change doesn't really do anything by itself since there's no software which observes and responds to these changes. Additionally, without CONFIG_HOSTCMD_ESPI_VW_SLP_S5, SLP_S5_SIGNAL_L is defined to SLP_S4_SIGNAL_L, so we're actually reporting changes of VW_SLP_S4 under this new power signal. In the next CL, we'll wire up the common SLP_S5 power signal to this virtual wire so that the power state machine can actually see changes on this line. A Cq-Depend line is added, though not technically necessary, to indicate this somewhat mind-melting state is only transient. BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Cq-Depend: chromium:3286185 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I77b1aad508eeae3b3f8b307d02cb98460341e6bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3310527 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* power: Introduce S4 as a real power stateEvan Green2021-12-012-11/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support hibernate (suspend to disk) on some systems, there are normally two choices for hibernate's destination power state: shutdown and S4. On most systems, shutdown is the logical choice for Chrome OS, since the wake sources are the same, and device state is properly saved/restored across an S5/G3 transition. However on Brya devices with Intel Keylocker technology, there is an IWKey (intermediate wrapping key) which software by design is not allowed to read. Intel, being no stranger to the concept of hibernate, provisioned support to save and restore this register in a platform area, while still keeping its contents inaccessible to software. However, architecturally they only guarantee this mechanism works down to S3/S4. This means in order to preserve keylocker contents during hibernation, shutdown is no longer an option. We must camp out in the architecturally designated S4 state during hibernation on devices with Intel Keylocker. The EC has long ignored this as a state since the OS doesn't support entering it. This needs to change. This patch introduces a POWER_S4 state. It's modeled after the S3 state, but represents itself as a "chipset soft off" state, like S5. Now, on Intel platforms, we (almost) always transition through S4 on our way up and down. For example, where we would normally go G3->S5->S3->S0, we now go G3->S5->S4->S3->S0. The "almost" refers to unusual error cases, where if power signals are totally wonky we may go from S3 straight to S5. The S3 <-> S5 state transitions also still exist because non-Intel platforms transition directly without going through S4. This bit of consistency was sacrificed to avoid retrofitting a bunch of ARM EC code to transition though a completely phony state. The "almost" refers to unusual error cases, where if power signals are totally wonky we may go from S3 straight to S5. The common Intel code used to look at SLP_S4 as a signal to transition between S5 and S3. Now, we look at SLP_S4 as the signal to transition to S4, and use the SLP_S5 signal to transition deeper, into S5. On platforms with virtual wire support, we should have access to the virtual SLP_S5 line already. On platforms that haven't explicitly set the config for VW_SLP_S5, we merge SLP_S5 and SLP_S4 by making them the same GPIO, so that the transition through S4 simply slides on through. This effectively disables S4 residency, so we disallow advertising S4 residency to the AP unless CONFIG_HOSTCMD_ESPI_VW_SLP_S5 is also enabled. We should then enable this on all new Intel platforms. Signed-off-by: Evan Green <evgreen@chromium.org> BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Change-Id: Icf4798fa517d40ad652a278bbea2051e4c9fb118 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3265286 Commit-Queue: Evan Green <evgreen@chromium.org> Tested-by: Evan Green <evgreen@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power/common.c: Merge state handling of S0/S3/S0ixEvan Green2021-12-011-10/+4
| | | | | | | | | | | | | | | | In power_common_state(), S0, S3, and S0ix all have the same thing in their cases. Merge them together in preparation for adding POWER_S4, which will yet again do the same thing. BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: If62fad7e93be8f1bcf4ec843c0ff236587116632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3286184 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* power: Add default cases for power state handlersEvan Green2021-12-018-0/+42
| | | | | | | | | | | | | | | | | In preparation for the addition of the new POWER_S4 state (and transition states) coming in, add default cases for ARM power state handlers, which won't be adding phony transitions through a non-existent S4 state. BRANCH=None BUG=b:204947672 TEST=hiberman hibernate --test-keys on volteer Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I48c884131037cbff917230134a34718c32ce75db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3286183 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power/mt8192: ignore ap-off flag when manual sysjumpTing Shen2021-11-251-2/+1
| | | | | | | | | | | | | | | | | | | | Use system_jumped_late() to distinguish EFS and non-EFS jump when initialization. BUG=b:207456321 TEST=dut-control power_state:rec # wait for DUT dut-control power_state:warm_reset verify AP can boot BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Id446c248454620eca87ffb3c61e6f732ae90a66b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3300170 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* intel_x86: Apply chipset resume init and suspend complete hooksDevin Lu2021-11-231-0/+18
| | | | | | | | | | | | | | | | | | | The CL:2321875 introduced a hook for chipset resume init and suspend complete. The application was applied for SPI driver for sc7180. This patch applies to intel_x86 as well. The benefit that we can initial the devices (such as PCHG) prior the chipset resume and shutdown the devices after the chipset suspend is completed. BUG=b:205675485 BRANCH=None TEST=make buildall -j Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I7ded958e1d2722b2e48c21466ff6fd2f82ecc5e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276030 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPIKeith Short2021-11-191-1/+1
| | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842 Tested-by: Michał Barnaś <mb@semihalf.com>
* falconlite: ensure WDT is deasserted when hard shutdown.Eric Yilun Lin2021-11-171-2/+9
| | | | | | | | | | | | | | | | | | | | There will be two cases when AP has a shutdown request: AP_EC_SHUTDOWN_REQ:1 AP_EC_WATCHDOG_L:1 -> This is a real shutdown request. AP_EC_SHUTDOWN_REQ:1 AP_EC_WATCHDOG_L:0 -> This is a WDT reset, and AP will handle this reboot, EC should not touch it. BUG=b:171029078 TEST=EC is able to handle AP's shutdown request. BRANCH=main Change-Id: Id89f3bc386dc73225731a96bafae48a55df06e73 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3270227 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* qcom: Add checks for EFS2 to the power on sequenceKeith Short2021-11-121-7/+16
| | | | | | | | | | | | | | | | | | | | | | | When EFS2 is enabled, the normal boot will always have the EC_RESET_FLAG_SYSJUMP set. Always enabled auto power on of the AP unless one of the following conditions is true: 1. EC_RESET_FLAG_AP_OFF reset flag is set 2. EC_RESET_FLAG_SYSJUMP reset flag is set, and EC_RESET_FLAG_EFS is not set. BUG=b:193719620 BRANCH=none TEST=Verify EC powers up AP after performing a sysjump when EFS2 is enabled. TEST=Set recovery mode, verify EC goes back to RO. On power down, EC jumps to RW and the AP stays in G3. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I222c5f6c729901b455888432cd01fe7e67b4aa7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3257770 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power: add casts for power signalsTom Hughes2021-11-123-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When building with clang, it warns: power/icelake.c:49:11: error: implicit conversion from enumeration type 'enum espi_vw_signal' to different enumeration type 'enum gpio_signal' [-Werror,-Wenum-conversion] .gpio = SLP_S4_SIGNAL_L, ^~~~~~~~~~~~~~~ include/power/intel_x86.h:40:25: note: expanded from macro 'SLP_S4_SIGNAL_L' Although "enum espi_vw_signal" and "enum gpio_signal" are not directly compatible, it appears that the code in power/common.c takes that into account by calling espi_signal_is_vw(). BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibb3ac42516d2e293cf707ca92eacd6bd7c11049c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3243003 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* power: Combine chipset_reset_reason and chipset_shutdown_reasonTom Hughes2021-11-1211-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | When building with clang, it warns: power/amd_x86.c:59:18: error: implicit conversion from enumeration type 'enum chipset_reset_reason' to different enumeration type 'enum chipset_shutdown_reason' [-Werror,-Wenum-conversion] report_ap_reset(reason); The two enums are already set up so that they don't overlap, so just combine them into a single enum. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => All boards match, except: burnet cerise damu fennel jacuzzi juniper kakadu kappa katsu kodama krane kukui makomo stern willow Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I47620e59e02a84c04dde4469f36ad37dccbcd9e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3238250 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* power/mt8192: remove unused variableTing Shen2021-11-111-3/+0
| | | | | | | | | | | | | | BUG=none TEST=makeall BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: If1199ed3ad87867c7d6ace54c0865369e6cf7638 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3275003 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* power/rk3399: Change fake GPIOTom Hughes2021-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | When building with clang, it warns: power/rk3399.c:605:26: error: implicit conversion from enumeration type 'enum power_signal' to different enumeration type 'enum gpio_signal' [-Werror,-Wenum-conversion] power_signal_interrupt(POWER_SIGNAL_COUNT); ~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~~~~~~~~~ It appears the intent is to derive a signal to send that is beyond the number of power signals, but "enum gpio_signal" and "enum power_signal" are separate enums, so POWER_SIGNAL_COUNT could be some other valid GPIO. Note that this is a functional change. BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=scarlet Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iba143e8903c11a4315e6b74fdb8e3245938b2b50 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3243007 Reviewed-by: Diana Z <dzigterman@chromium.org>
* power: support falcon-lite power sequencingEric Yilun Lin2021-11-052-0/+509
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy and modified from power/mt8192.c There's no PMIC in falcon-lite, and EC has to control the rails. Besides PGOOD signals, and power enable pins, the important rails are: - AP_EC_WARM_RST_REQ: AP issues a warm reset request and EC toggles SYS_RST_ODL for a S0->S0 transition. - AP_EC_SHUTDOWN_REQ_L: This pin is repurposed from AP_IN_SLEEP_L. AP issues a shutdown request and EC forces it in to off state. - AP_EC_WATCHDOG_L: This pin is unused since AP is able to reset itself when WDT happened. There's no S3 signals for falcon-lite since AP_IN_SLEEP_L is repurposed, so we used host power info for S3/S0 transition. BUG=b:185846337 TEST=Tried the following cases: * Cold reset: $ dut-control cold_reset:on sleep:0.2 cold_reset:off Result: G3 -> S0 * Long power press to shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: S0 -> S5 -> G3 * Long power press to power-on but then shutdown: $ dut-control pwr_button:press sleep:8.2 pwr_button:release Result: G3 -> S0 -> S5 -> G3 * Short power press to power-on: $ dut-control pwr_button:press sleep:0.2 pwr_button:release Result: G3 -> S0 * Console command: apreset Result: S0, AP reboots * Console command: apshutdown Result: S0 -> S5 -> G3 * Lid open to power-on: $ dut-control lid_open:no sleep:0.2 lid_open:yes Result: G3 -> S0 BRANCH=main Change-Id: I239975513286b062f80184f91e565d2bd6fa01ac Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045436 Tested-by: Eric Yilun Lin <yllin@google.com> Auto-Submit: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* zephyr: mt8192: gather power-signal information from DTDenis Brockus2021-11-031-0/+4
| | | | | | | | | | | | | | | | | | This currently only uses DT power-signal for platforms that define CONFIG_AP_ARM_MTK_MT8192 BUG=b:188674805 BRANCH=none TEST=zmake testall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I151c451f0725449459744b1ebda042c0c3aa6ad8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246296 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* power/common.c: Add explicit cast when converting between enum typesTom Hughes2021-10-291-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns: power/common.c:118:28: error: implicit conversion from enumeration type 'enum gpio_signal' to different enumeration type 'enum espi_vw_signal' [-Werror,-Wenum-conversion] return espi_vw_get_wire(signal); ~~~~~~~~~~~~~~~~ ^~~~~~ power/common.c:128:36: error: implicit conversion from enumeration type 'enum gpio_signal' to different enumeration type 'enum espi_vw_signal' [-Werror,-Wenum-conversion] return espi_vw_disable_wire_int(signal); ~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~ power/common.c:138:35: error: implicit conversion from enumeration type 'enum gpio_signal' to different enumeration type 'enum espi_vw_signal' [-Werror,-Wenum-conversion] return espi_vw_enable_wire_int(signal); The conversion appears to be intentional, so add an explicit cast. BRANCH=none BUG=b:172020503 TEST=make CC=arm-none-eabi-clang BOARD=elm -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ide2abc115957385097f6ed938b0a15139cbf3d83 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3197755 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* board: Rename RSMRST_L_PGOOD as PG_EC_RSMRST_ODLfirmware-chameleon-14280.B-mainDivya Sasidharan2021-10-124-7/+7
| | | | | | | | | | | | | | | | | GPIO_RSMRST_L_PGOOD is also used as GPIO_PG_EC_RSMRST_ODL creating redundancy. Removing it will help need for redefinitions for zephyr. Remove reference to GPIO_RSMRST_L_PGOOD in zephyr BUG=b:200975143 BRANCH=main TEST=make buildall -j, boot up on brya Change-Id: Iff46595174c54db347b69cff3ad9e266ba9fd535 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180808 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* power/mt8192: set correct initial power state for EFS2Ting Shen2021-10-121-1/+2
| | | | | | | | | | | | | | | | | | | | | In EFS2, the boot flow happens in RW, so we should not set power state to S0 by default. BUG=b:185726892 TEST=1. Verify AP bootable and able to update EC-RW in following scenarios: a. old RW b. corrupted (not-bootable) RW 2. DISABLE_EC_SOFTWARE_SYNC vboot flag works. 3. manual sysjump won't reboot AP. BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ic088a1ccf80fc49424cc1eeb3ff7b946836e5b68 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3207813 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* power/alderlake: Cleanup code to use common GPIO nameDivya Sasidharan2021-10-051-7/+7
| | | | | | | | | | | | | | | | | | SEQ_EC_ALL_SYS_PG is commonly named as PG_EC_ALL_SYS_PWRGD. Removing it to reduce the redundant declarations needed in zephyr. BUG=b:200975143 BRANCH=main TEST=make buildall -j; boot up brya Change-Id: Ie266460dfe9c61dbbb97e1d1b714824929c5a098 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180807 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* host sleep: fix infinite timeoutBoris Mittelberg2021-09-241-1/+3
| | | | | | | | | | | | | | | | | | | | Add the corner case when default == infinite BUG=b:187532888 BRANCH=none TEST=manual: 1. `/usr/share/vboot/bin/make_dev_ssd.sh --edit --part=2` 2. Add `intel_idle.max_cstate=1` 3. reboot 4. (EC) `sleeptimeout infinite` 5. `echo freeze > /sys/power/state` 6. System doesn't wake up Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I5903ddd09262254a485eb9d09731bcd687b6d650 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180260 Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* qcom: Deprecate WARM_RESET handlings in SC7280Wai-Hong Tam2021-09-171-10/+15
| | | | | | | | | | | | | | | | Add guards to limit the long warm_reset handling only in SC7180, such that the future generations, like SC7280, don't have it. BRANCH=None BUG=b:187980397, b:187098628 TEST=Built all the Chromium EC images and Zephyr EC images. TEST=Modify a board to use the SC7280 CONFIG. Change-Id: Iad011f58522641cde2f469f71114473476c53d67 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893070 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* herobrine: Always enable the 5V railWai-Hong Tam2021-09-161-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare the next hardware revision. It has a PPC chip which requires 5V rail in S5. The 5V rail enable pin should be turned on whenever the EC is powered. Since the existing 5V rail enabling is done inside the qcom power sequence. Trogdor and Herobrine both shares this qcom power sequence. For Trogdor, this CL moves the 5V rail enabling from the qcom power sequence to the board level hook. For Herobrine, this CL updates the GPIO name and modifies the default level to HIGH. The CONFIG of 5V control should be disabled. As no board level hook to modify the 5V rail, the 5V is always on. BRANCH=None BUG=b:199804198 TEST=Booted both Zephyr and EC-OS images on Herobrine. Checked the 5V rail is enabled in S0 and S5. TEST=Booted both Zephyr and EC-OS images on Lazor. Checked the 5V rail is enabled in S0 and disabled in S5. Change-Id: Ifa98ee0c4e970dd89952e94cc6a0e289798e6a57 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163918 Reviewed-by: Keith Short <keithshort@chromium.org>
* power: Fix host_command_hibernation_delay returnTomasz Michalec2021-09-031-1/+1
| | | | | | | | | | | | | | | host_command_hibernation_delay() should return enum ec_status and correct value of this type to indicate success is EC_RES_SUCCESS BUG=none BRANCH=none TEST=none Signed-off-by: Tomasz Michalec <tm@semihalf.com> Change-Id: I50902829a7ef5d09786ab81bff9d791bac0dfad6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140204 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* qcom: Increase the delay between powering on the switchcap and the PMICWai-Hong Tam2021-08-121-2/+5
| | | | | | | | | | | | | | Measured the delay on Herobrine IOB + Trogdor MLB is ~200ms. Pick a larger delay 300ms. BRANCH=None BUG=None TEST=Booted AP successfully. Change-Id: Iaba20995e23c2f2041601c9fc17f35a1cb9300c4 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3083184 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* qcom: Move enabling/disabling 3.3V rail to the board levelWai-Hong Tam2021-07-141-4/+2
| | | | | | | | | | | | | | | | | | | | | | In the next generation, the 3.3V rail is not controlled by EC anymore. Move the control logic to the board level. The 3.3V rail should be enabled before the power on sequence, so use the hook chipset pre-init hook. Disable it on the chipset shutdown complete hook. For Trogdor, do it on the baseboard level. For Herobrine, do it on the board level, Herobrine-NPCX7, only. Herobrine-NPCX9 and other future boards don't need it. BRANCH=None BUG=b:187980397, b:192253134 TEST=Tested the Lazor EC-OS and Zephyr images and booted to AP. TEST=Tested the Herobrine-NPCX7 EC-OS and Zephyr images and booted to AP. Change-Id: I7e025123f8997629b9b0db46e30ea9c716bdbf99 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993213 Reviewed-by: Keith Short <keithshort@chromium.org>
* qcom: Deprecate AP_RST_REQ in SC7280Wai-Hong Tam2021-07-131-0/+2
| | | | | | | | | | | | | | | Add guards to deprecate the AP_RST_REQ power signal. The AP_RST_REQ is power signal only valid in SC7180. BRANCH=None BUG=b:187980397, b:148246695 TEST=Built all the Chromium EC images and Zephyr EC images. TEST=Modify a board to use the SC7280 CONFIG. Change-Id: I0b12889dd2549665d2c2d6bfc06fddd9b9357175 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993210 Reviewed-by: Keith Short <keithshort@chromium.org>
* Power: Cast hibernate delay before converting to microsecondsDiana Z2021-07-121-1/+2
| | | | | | | | | | | | | | | | If the hibernate delay has been configured to be very large, then the conversion into microseconds may overflow a uint32_t. So cast before multiplying. BRANCH=None BUG=b:190056419 TEST=on guybrush, confirm target is in the correct range (i.e. 2 months from now) Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I449b0d14418cb119080e2e03960a3a31fab4bf2b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3018450 Reviewed-by: Rob Barnes <robbarnes@google.com>
* AMD: Ignore forced shutdown if transitioningDiana Z2021-07-021-1/+1
| | | | | | | | | | | | | | | | | | | Ignore new forced shutdown requests if we're in the process of transitioning to off already. Otherwise, the power button press may turn the system back on again. BRANCH=None BUG=b:192463842 TEST=on guybrush, run the battery down to 2% in S0 and observe that we can successfully enter G3 even when additional chipset_force_shutdown() commands come through during the transition Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie2c83db939fe1cc8b3258903e209cba6394027fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000849 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* kukui: enable HOST_SLEEP_STATE to smooth suspend trasnsitionEric Yilun Lin2021-06-291-0/+71
| | | | | | | | | | | | | | | | | To smooth the suspend transition to prevent from EC waking up AP during S0->S3. BUG=none TEST=ensure AP notify EC before suspending BRANCH=kukui,icarus Change-Id: I6d4d79be2688c53e0057f5e60a394cfa8974e501 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987228 Tested-by: Eric Yilun Lin <yllin@google.com> Auto-Submit: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* power: Reorder the power_chipset_init and the interrupt enableWai-Hong Tam2021-06-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous order is: * power_chipset_init() * enabling/disabling the power signal interrupts There is a need that power_chipset_init() modifies the power signal interrupt enabling/disabling, like crrev.com/c/2977573. The power_chipset_init() checks if AP is ON or OFF; when AP is OFF, a power signal interrupt is disabled (default) to avoid the floating interrupt storm; but when AP is ON, the power signal interrupt is enabled. But the next action resets the interrupt to default. This CL reorders it to: * enabling/disabling the power signal interrupts * power_chipset_init() So the interrupt enable/disable status won't be overridden. BRANCH=None BUG=b:185551931 TEST=Tested on Coachz, reboot EC, sysjump to RW, perform `apreset` which executes a warm AP reboot. Change-Id: I1740fed1d37a312ac822b2a91e9ebd5502756a1f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2986224 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: asurada: move power/it8xxx2 to be in power/mt8192Denis Brockus2021-06-223-15/+10
| | | | | | | | | | | | | | | | | | | | The power_signal_list was mistakenly moved to a new file power/it8xxx2.c and is used by both zephyr and cros-ec. This moves the content of this file into where it belongs at power/mt8192.c BUG=b:180980668 BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I687f097bee37ac5211c3a7d04019e2dd70207889 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980111 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
* qcom: Enable AP_RST_L interrupt on sysjump to RWWai-Hong Tam2021-06-221-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The AP_RST_L interrupt is default disabled. It avoids unnecessary power signal messages in G3/S5 as the signal is floating (no power). The interrupt is then enabled during S5->S3 and disabled during S3->S5. However, when sysjump to RW, the interrupt is back to default disabled. This causes the `apreset` command fails to sample the AP_RST_L signal and forces to execute a cold reboot sequence. We should enable AP_RST_L interrupt when the initial power state is S0, the sysjump to RW scenario. BRANCH=Trogdor BUG=b:185551931 TEST=Tested on Coachz, reboot EC, sysjump to RW, perform `apreset` which executes a warm AP reboot. Change-Id: I7eae5f2bcacfebeeee529aa7ad96409cfe9122e9 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977573 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* asurada: enable HOST_SLEEP_STATE to smooth suspend trasnsitionEric Yilun Lin2021-06-151-0/+70
| | | | | | | | | | | | | | | | | | | | | | | MT8192 previously didn't enable the command due to it already has AP_IN_SLEEP_L, but we found that if we don't have the command, EC might have rare chance to interrupt AP with hostevent when AP in transition to S3, and cause the suspend failure. This CL enables CONFIG_POWER_TRACK_HOST_SLEEP_STATE so the EC is able to handle the AP's hint to disable non-wakeup hostevent when it's transisting to S3. BUG=b:186709406 TEST=ensure EC received the AP's note BRANCH=asurada Change-Id: I7a2a7eefc7620817ca446fd24370375130daf6be Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2954984 Tested-by: Eric Yilun Lin <yllin@google.com> Auto-Submit: Eric Yilun Lin <yllin@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* host sleep: add command to change sleep fail detection timeoutBoris Mittelberg2021-05-261-1/+46
| | | | | | | | | | | | | | | sleeptimeout is a new EC console command to change S3/S0ix sleep fail detection timeout. Needed for debug only. The command is present only if CONFIG_POWER_SLEEP_FAILURE_DETECTION is defined BRANCH=none BUG=b:187532888 TEST=manual Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I9a2afbb89dbfb4bdaf8666e06cf810e7cace9aad Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904896 Reviewed-by: caveh jalali <caveh@chromium.org>
* qcom: Deprecate QSIP_ON, a load switch enableWai-Hong Tam2021-05-221-9/+0
| | | | | | | | | | | | | | | | | | QSIP_ON is only valid on Trogdor rev-1. It controls the load switch enable. The load switch is used for experiments but leaving it off consumes power. On other Trogdor boards, QSIP_ON is just NC. Since we no longer support Trogdor rev-1, deprecate the control in the power sequence. BRANCH=None BUG=b:159999589 TEST=Build the Trogdor image. Change-Id: Ie5f04ed3de5f14ba32a92fa8223e8769bb97cf82 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911505 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* zephyr: asurada: Enable power button and sequencingDenis Brockus2021-05-192-1/+15
| | | | | | | | | | | | | BUG=b:180980668 BRANCH=none TEST=get powerbtn command in shell Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I1af4673b7eff84149e3aabad7ff09445a1f96e1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2895306 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* qcom: Create new configs for SC7280Wai-Hong Tam2021-05-181-0/+1
| | | | | | | | | | | | | | | Create new configs (Chromium EC namespace and Zephyr namespace) for SC7280. In this state, SC7280 power sequence has no difference from SC7180. BRANCH=None BUG=b:187980397 TEST=Built all the Chromium EC images and Zephyr EC images. TEST=Modify a board to use the new CONFIG. Change-Id: I178b8ffa5d79d3828baf222ac77906ab2262cf76 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893069
* qcom: Generalize the power signals and functions for SC7x80Wai-Hong Tam2021-05-171-14/+14
| | | | | | | | | | | | | Rename the power signals from SC7180 to SC7X80. Rename the functions. BRANCH=None BUG=b:187980397 TEST=Built all the Chromium EC images and Zephyr EC images. Change-Id: Icf932b5cc892dcc9e57bff10bdd6db8d532f24a9 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893485 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* qcom: Generalize the filenames for Qualcomm chipsetsWai-Hong Tam2021-05-173-3/+3
| | | | | | | | | | | | | | | The existing SC7180 power sequence can be reused on its next generation. Generalize the filenames, sc7180.c/sc7180.h to qcom.c/qcom.h. BRANCH=None BUG=b:187980397 TEST=Built all the Chromium EC images and Zephyr EC images. Change-Id: Ie04218ef0a12a4e8aa2db353040c5c39c533ae6f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893484 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* amd_x86: Check for S0ix before S3Rob Barnes2021-04-271-3/+6
| | | | | | | | | | | | | | | Cezanne is asserting both SLP_S0 and SLP_S3 for S0ix. On Intel only SLP_S3 is asserted. Move check for S0ix before check for S0 so EC enters correct power state. BUG=b:186135411 TEST=EC reports S0ix power state BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I47ede14e8031ba4d6a01399f2501801e597a6b1f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847332 Reviewed-by: Diana Z <dzigterman@chromium.org>
* AMD Power: Remove reference to S5 pauseDiana Z2021-04-121-3/+0
| | | | | | | | | | | | | | | | | The AMD power states don't actually reference the S5 pause variable, and instead always pause in S5 when power transitioning. It appears only braswell and samus power transitions actually use this pause to change their power sequencing. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0bdaa714fa41a696a8e446b04a62aba793e59432 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2818527 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* Power: Add configurable S5 timeoutDiana Z2021-04-101-5/+39
| | | | | | | | | | | | | | | | Similar to the hibdelay command, allow the time we spend in S5 to be configurable for the sake of power testing in this state. It may be set to 0 for an immediate drop, or -1 to stay in S5 forever. BRANCH=None BUG=b:184941436 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If2f8cf91ba982822e2e33cb17f84f38c40907d2e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2818526 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* alderlake: Remove resolved TODOCaveh Jalali2021-04-021-4/+1
| | | | | | | | | | | | | | This removes a TODO for b/179524867. We have determined that no special handling needs to be performed in chipset_handle_espi_reset_assert. BRANCH=none BUG=b:179524867 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I6d40b6119e3bef613e5ba2d9adfa986b79be9078 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2798982 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* power: change pwr_5v_ctl_mtx to use K_MUTEX_DEFINEJack Rosenthal2021-03-231-7/+1
| | | | | | | | | | | | | | Use K_MUTEX_DEFINE() to automatically initialize this mutex, removing the requirement to call k_mutex_init(). BUG=b:177677037 BRANCH=none TEST=zmake testall && make buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I2873f5bd46788b24442f0121377abb3132be2622 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2782234 Reviewed-by: Simon Glass <sjg@chromium.org>
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