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* charge_manager: Pass uncapped / max current to current limit callbackShawn Nematbakhsh2016-09-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | charge_manager may request a charge current limit less than the capability of the supply in certain cases (eg. during PD voltage transition, to make an effort to comply with reduced load spec). Depending on the battery / system state, setting a reduced charge current limit may result in brownout. Pass the uncapped / max negotiated current to board_set_charge_limit() so that boards may use it instead of the requested limit in such circumstances. BUG=chrome-os-partner:56139 BRANCH=gru TEST=Manual on kevin with subsequent commit, boot system with zinger + low-charge battery, verify devices powers up to OS without brownout. Change-Id: I2b8e0d44edcf57ffe4ee0fdec1a1ed35c6becbbd Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383732 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: motion_lid: Add tablet mode detection using lid angle.Gwendal Grignou2016-09-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | Using the lid angle, detect if we are in tablet mode or not. We are in tablet mode when the lid angle is large enough: tablet_mode: 1 | +-----<----+---------- | \/ /\ | | | 0 |------------------------>----+ +------------------+----------+----------+ lid angle 0 240 300 360 BRANCH=kevin BUG=chrome-os-partner:55702,b:27849483 TEST=Check on Kevin event are sent on tablet mode transition. Change-Id: Id9935ce4dd717e2c20fa6c9520defb504a1760d9 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/383073 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* motion_lid: prevent angle 0 <-> 360 transition.Gwendal Grignou2016-09-092-0/+28
| | | | | | | | | | | | | | When lid is closed, the lid angle can move to 358, 360, 0, 359 ... Prevent transition 0 from/to 360 by keeping the last calculated value. BRANCH=kevin BUG=chrome-os-partner:55702 TEST=Check transition does not happen anymore. Change-Id: Ifa8415470f425c893e2c3662c84c8fd0156e0524 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373040 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: NvMem: Allow for partitions to not be contiguousScott2016-09-022-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | TPM2.0 needs more NvMem space and currently the whole block is contiguous in memory with 2 partitions. This CL removes the requirement that the partitions are in contiguous which allows for 1 partition to placed at top of RW_A and the other at RW_B. This CL does not change the size of each partition as that will be done in a subsequent CL. BRANCH=none BUG=chrome-os-partner:56798 TEST=manual Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and verified that all tests pass. Tested on Kevin, erased the existing NvMem area and verified that TPM was still manufactured and executed the command: trunks_client --own Erased parition 0 and 1 in the new locations and repeated the tests. Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378675 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add tests for dcrypto bn_modinv_vartimenagendra modadugu2016-09-026-7/+189
| | | | | | | | | | | | | | | | | | | This change introduces a larger range of tests for bn_modinv_vartime. The tests are designed to run on a host, and compare results against openssl. BRANCH=none BUG=chrome-os-partner:47524 TEST=bn_test passes Change-Id: I2d6ea4824fa82f78f8797c0cfc2cf0dce03e8923 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/365232 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* test: Properly exclude CONFIG_POWER_TRACK_HOST_SLEEP_STATEShawn Nematbakhsh2016-09-021-1/+0
| | | | | | | | | | | | | | | | | | CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on CONFIG_POWER_COMMON, so remove it from test builds that don't have a chipset task, rather than heavy-handedly removing it from all test builds. BUG=chrome-os-partner:56197 BRANCH=None TEST=`make BOARD=gru tests` Change-Id: I86e20b4dccbb01ee285054a47093d6f60abc2166 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/378119 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* CR50: add tests for AES CBC, CFB and OFBnagendra modadugu2016-08-253-7/+541
| | | | | | | | | | | | | | | | | | | | | | | Add tests for CBC, CFB and OFB AES modes. Also convert tests to use word unligned input parameters, to ensure that the api's are unalignment agnostic. Also add the program used for generating test vectors. BRANCH=none BUG=chrome-os-partner:56413 TEST=tpmtest.py passes Change-Id: I92c9ffece797aa7134d9cdad6ea32e6fe50feef1 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/374663 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* test: motion_lid: Use new sensor frameGwendal Grignou2016-08-242-36/+17
| | | | | | | | | | | | | Update motion_lid to use Android/HTML5 vector frame for sensor. BUG=none BRANCH=none TEST=Test motion_lid passes. Change-Id: Ic4484e716b678b8399b058ade2bc13480f6cf393 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/373724 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Correct interpolation algorithm of thermal values.Ravi Chandra Sadineni2016-08-171-32/+32
| | | | | | | | | | | | | | | Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> BRANCH=none BUG=chrome-os-partner:56206 TEST=make buildall -j Change-Id: I22ac65f33b27b8ce8ad0687971f47b82395aa781 Reviewed-on: https://chromium-review.googlesource.com/370402 Commit-Ready: David Hendricks <dhendrix@chromium.org> Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org> Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* pd: fix CC values in usb PD unittestsVincent Palatin2016-08-161-6/+4
| | | | | | | | | | | | | | | | | The if conditions to simulate the CC line levels had a couple of typos. Use a more realistic value for those corner cases. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make run-usb_pd Change-Id: Ia924ee4cfe4512a7543cfcae4d532c9a250d9c8d Reviewed-on: https://chromium-review.googlesource.com/368720 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* test: Don't test with CONFIG_POWER_TRACK_HOST_SLEEP_STATEShawn Nematbakhsh2016-08-121-2/+2
| | | | | | | | | | | | | | | CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on MKBP, so just remove it from tests. BUG=chrome-os-partner:56156 BRANCH=None TEST=`make BOARD=gru tests` Change-Id: I8b95954e106c28c7152666c510f7611fe87014a0 Reviewed-on: https://chromium-review.googlesource.com/368970 Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* Cr50: NvMem: Added write/move error stateScott2016-08-111-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvmem_write() and nvmem_move() funcitons return an error if the write or move operation would exceed the user buffer boundary. However, the TPM2 functions which call these functions do not check for errors. Instead TPM2 NvMem relies on the return value of the nv_commit() function to determine if a TPM command which modifies NvMem succeeds or fails. This CL adds a nvmem_write_error flag which is set in cases where an nvmem_write/nvmem_move returns an error. This error flag is then checked in nvmem_commit() so that the commit operation can be abandonded and the error returned back up the TPM2 stack. Tested in full system for two cases. Installed TPM certificates on the Cr50, then manually erased NvMem with flasherase 0x7b000 0x5000 and rebooted system. Then on Kevin console entered the command <trunks_client --own> NV_MEMORY_SIZE = 9932 NVMEM_TPM_SIZE = 7168 Case 1 -> Without internal write error state, so commit() always executes if called. In this case, the Kevin console reports a TRUNKS_RC_WRITE_ERROR and there is a Cr50 reboot. Kevin Console: localhost ~ # trunks_client --own [INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK. [INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK. [ 134.056217] tpm tpm0: Operation Timed out [ERROR:tpm_utility_impl.cc(1987)] DoesPersistentKeyExist: querying handles: TRUNKS_RC_WRITE_ERROR [ERROR:tpm_utility_impl.cc(269)] TakeOwnership: Error creating salting key: TRUNKS_RC_WRITE_ERROR [ERROR:trunks_client.cc(98)] Error taking ownership: TRUNKS_RC_WRITE_ERROR Cr50 Console: > [131.501920 nv_commit()] [142.494755 nv_wr: max off = 0x1250] [142.496347 nv_wr: max off = 0x17b4] [142.548296 nv_commit()] [142.678001 nv_rd: max off = 0x1250] [142.679350 nv_rd: max off = 0x1254] [143.269614 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [143.271460 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [143.273055 Wr Err = TRUE, Resetting error only, not returning] [143.325073 nv_commit()] --- UART initialized after reboot --- [Reset cause: rtc-alarm] [Image: RW_B, cr50_v1.1.5056-8e5dc99+ private-cr51:v0.0.69- 12:23:02] [0.004349 Inits done] [0.007150 Active NVram partition set to 0] [0.008086 Debug Accessory connected] [0.009076 USB PHY B] Console is enabled; type HELP for help. tpm_manufactured: manufactured [1.155766 usb_reset] [1.240155 usb_reset] [1.311188 SETAD 0x6c (108)] Case 2 -> Using internal error state to gate the commit() operation. In this case, the attempted write overflow sets the internal error state and the commit() following attempted overflow detection is not exectued. It results in a different AP TPM error shown below as Error encrypting salt. The other different behavior is that observed is that if after failing on the RSA SRK, the ECC SRK write is still attempted. Kevin Console: localhost ~ # trunks_client --own [INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK. [INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK. [ERROR:session_manager_impl.cc(154)] Error fetching salting key public info: Handle 1: TPM_RC_HANDLE [ERROR:session_manager_impl.cc(94)] Error encrypting salt: Handle 1: TPM_RC_HANDLE [ERROR:tpm_utility_impl.cc(277)] TakeOwnership: Error initializing AuthorizationSession: Handle 1: TPM_RC_HANDLE [ERROR:trunks_client.cc(98)] Error taking ownership: Handle 1: TPM_RC_HANDLE Cr50 Console: > [107.867473 nv_commit()] [133.743522 nv_wr: max off = 0x123f] [133.744908 nv_wr: max off = 0x1250] [133.746159 nv_wr: max off = 0x17b4] [133.798498 nv_commit()] [133.900131 nv_rd: max off = 0x1250] [133.901496 nv_rd: max off = 0x1254] [134.507033 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [134.508852 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [134.510440 Wr Err = TRUE, Aborting Commit!] [144.856751 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [144.858611 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [144.860198 Wr Err = TRUE, Aborting Commit!] BRANCH=none BUG=chrome-os-partner:55910 TEST=manual Test in system as described above and ran NVMEM unit tests and verified that when a write would overrun the user buffer, the write fails and sets the error state. Then, verified that the nv_commit() call returns an error and clears the internal error state. Change-Id: I376e17b273003ff3d75459b4e68ed69d42dc7415 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366757 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ec: Unit test: Remove (temporarily) nvmem from test-list-hostScott2016-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There seems to be flaky issue where the nvmem tests don't fully complete. I need to spend some time to try and understand the mechanism. It doesn't happen on every build attempt and never happens when I just run this particular test. In the meantime, I don't want the builder to fail due to this issue so I am removing this test from the test-list-host while I debug the issue. BUG=chrome-os-partner:55854 BRANCH=none TEST=manual Execute the command 'make runtests' in /platform/ec and verified that the nvmem test is no longer executed. Change-Id: I9f0778fd9fa17cf8949292f7abe8b05ccab2bae2 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367302 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Rename EXTENSION_EC to EXTENSION_ECCBill Richardson2016-08-072-27/+27
| | | | | | | | | | | | | | | | | | | I keep thinking this refers to "Embedded Controller" instead of "Elliptic Curve Cryptography". Make it clearer. There's no functional change, I'm just renaming a constant. BUG=none BRANCH=none TEST=make buildall; run tests on Cr50 dev board make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py Change-Id: Iaf2e2839e88fdbbcb1a712934be56a0dd47e4a70 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366752 Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tpm: TPM_FW_VER returns chip ID and board revisionBill Richardson2016-08-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | The chip revision and board version show up on the second line of the returned string, immediately before the build info. BRANCH=none BUG=chrome-os-partner:55558 TEST=Queried version string using tpm_test make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 RO_A:* 0.0.2/d0c9abe3 RO_B: 0.0.2/13eda43f RW_A: cr50_ [...] B2:0 cr50_v1.1.5013-ab0e228+ [...] ^^^^ Change-Id: Iaa1efe5dca441aca24f281f76c1f218e24c844be Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/365421 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* thermistor: Add generic linear interpolation algorithmDavid Hendricks2016-08-011-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | The existing algorithm makes several assumptions for a particular thermistor circuit. This patch introduces a more generic version that can be used for multiple thermistors on a single board. The idea is to approximate a curve produced by solving for voltage measued by an ADC using the Steinhart-Hart equation. For a straight line one only needs two data points. For a steady curve data points can be distributed evenly. For the most part, though, data points should be provided after a significant change in slope. More data points give more accuracy at the expense of memory, and we mostly only care about accuracy in the range between "warm" and "too hot" so only a few data points should be used. BUG=chrome-os-partner:54818 BRANCH=none TEST=added unit test, needs real testing Change-Id: I046e61dbfd1e8c26c2a533777f222f5413938556 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344781 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Don't build native tests for this targetBill Richardson2016-07-281-0/+3
| | | | | | | | | | | | | | | The ancient native tests can't deal with board-specific configurations, don't build them. We run generic changes with host tests and board-specific cases by running on real hardware. BUG=chrome-os-partner:55705 BRANCH=none TEST=make BOARD=cr50 tests; make buildall; test on Cr50 hardware Change-Id: I5eb7229ca9df16293d6f0f84b474d4c992277baf Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363942 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: re-enable rsa 1024-bit keygen testnagendra modadugu2016-07-281-2/+1
| | | | | | | | | | | | | | | | Re-enable the RSA 1024-bit keygen test, which was fixed by change 76ab8e6f448a3fa3f216b1c54e8a0ca4ff282a08. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 BUG=chrome-os-partner:53893 TEST=test/tpm_test/tpmtest.py passes Change-Id: Id46bcf4ce4468928bd5256a5aadbf5b62419a6e1 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/364240 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: Improve version info for dual RO & RW imagesBill Richardson2016-07-261-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SoC looks for two RO images at reset, and is typically configured for two RW images as well. This CL reports version strings for all those images, as well as identifying the active RO and RW copies. Since the RO image doesn't contain a version string, we create one using the epoch_, major_, minor_, and img_chk_ members of its signed header. BUG=chrome-os-partner:55558 BRANCH=none TEST=make buildall; run on Cr50 hardware The "version" command now includes information like this: RO_A: * 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1.4965-a6c1c73-dirty RW_B: * cr50_v1.1.4959-2f49d5c The '*' indicates the active image. The test/tpm_test/tpmtest.py program has been updated to request the version information at startup, and it also now reports similar information, just all on one line: RO_A:* 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1 ... The active images are marked with a '*' following the ':', so that the same regexp can match either format: ($ro, $rw) = m/RO_[AB]:\s*\*\s+(\S+).*RW_[AB]:\s*\*\s+(\S+)/s; Change-Id: Ic27e295d9122045b2ec5a638933924b65ecc8e43 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362861 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: NvMem: Modified nvmem_init to handle 2 corrupt partitionsScott2016-07-221-7/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | During initialization the NvMem module looks for either a valid partition or that the NvMem area is fully erased. If neither of these two conditions were found, then it was only returning an error code and logging a message to the console. This CL modifies nvmem_init() so that if the error case as described above is detected, then it will call nvmem_setup() which will create two valid partitions. In addition, the setup function erases all of the existing data in the NvMem space. Enhanced the unit test that deals with both partitions being corrupted so that it verifies the version numbers are correct and that all user buffer data is set to 0xff. BUG=chrome-os-partner:55536 BRANCH=None TEST=Manual Executed make runtests TEST_LIST_HOST=nvmem and verifed that all tests passed. Change-Id: Ib932e02f15bd1aad7811032a12d826c76476e53f Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362448 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mkbp: Add support for buttons and switches.Aseda Aboagye2016-07-192-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the matrix keyboard protocol does not have support for handling non-matrixed keys. This commit adds support for buttons which do not appear in the keyboard matrix as well as switches. Additionally, the keyboard FIFO is now just a general MKBP events FIFO which MKBP events are free to use. Now, buttons and switches wil join the key matrix event. BUG=chrome-os-partner:54988 BUG=chrome-os-partner:54976 BUG=chromium:626863 BRANCH=None TEST=Flash kevin, and verify that keyboard is still functional. TEST=make -j buildall CQ-DEPEND=CL:358926 Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/358633 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm test: use proper locality zero SPI bus addressesnagendra modadugu2016-06-301-5/+7
| | | | | | | | | | | | | | The fix for SPI bus base address missed the tpm test driver, this patch fixes the issue. BRANCH=none BUG=chrome-os-partner:54720 TEST=tpmtest.py connects over ftdi & tests pass Change-Id: I5a59a6e089aee5a7c25466e0d183f3647c67343a Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356556
* CR50: add a golden test for RSA key gen from a fixed seednagendra modadugu2016-06-291-6/+9
| | | | | | | | | | | | | | | | Add a test that verifies RSA keygen from a fixed seed and template from the TCG EK Credential Profile spec. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpmtest pass Change-Id: I2f1cfb8460a0497c93079b89b9ff4e031eaff358 Reviewed-on: https://chromium-review.googlesource.com/356561 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Decouple temp sensor from thermal throttlingMary Ruthven2016-06-281-0/+1
| | | | | | | | | | | | | | | Not everything with a temperature sensor uses thermal throttling. This change modifies the conditional build to enable building temp sensor source without thermal throttling. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356484 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: NvMem: Added mutex lock protection for cache memoryScott2016-06-222-1/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added mutex lock for nvmem write/move operations. In the current implementation, there is no single entry point for the platform specific NvMem calls. The mutex lock is coupled with a task number so that the same task can attempt to grab the lock without stalling itself. In addition to the mutex lock, changed where the cache.base_ptr variable is updated. Previously, this was done prior to the partition being copied from flash to the shared memory area. Now, the variable is only updated after the copy so that read operations will always read from the correctly from either flash or from cache memory if a write operation has been started. BRANCH=none BUG=chrome-os-partner:52520 TEST=Manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass. Tested with tcg_test utility to test reads/writes using the command "build/test-tpm2/install/bin/compliance --ntpm localhost:9883 --select CPCTPM_TC2_3_33_07_01". Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353026 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add a simple ASN.1 parser & certificate verifierstabilize-8447.Bnagendra modadugu2016-06-121-1/+25
| | | | | | | | | | | | | | | | | Add a certificate verifier, so that endorsement certificates may be verified upon installation. Doing so allows for catching certificate errors early. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: I9339a6bc36e4d82ae875ce774e31848ae983fa1f Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/351031 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add tests for 1024-bit RSA.nagendra modadugu2016-06-011-6/+16
| | | | | | | | | | | | | | | | | | | | Add tests for RSA-1024, and created partner CRBUG/53893 to track issue discovered with 1024-bit modinv. 1024-bit RSA support being added in preparation for a forthcoming hardware based implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53893 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: I6b5aaeffc9df1cbbe403535fd21cdd377b42c38e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/348490 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: NvMem: Connected function stubs in /board/tpm2/NVMem.cScott2016-05-261-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | Used #define CONFIG_FLASH_NVMEM to have functions in /board/tpm2/NVMem.c utlitize on chip Nvmem functions. On chip NV Memory availability is tied to an internal nvmem error state which itself only depends on finding at least one valid partition. Added nvmem_is_different and nvmem_move functions which were needed to complete the tpm2 platform interface. In addition, added unit tests to support these two new functions. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass. Tested with tcg_test utility to test reads/writes using the command "build/test-tpm2/install/bin/compliance --ntpm localhost:9883 --select CPCTPM_TC2_3_33_07_01". Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/346236 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* NvMem: Added NV Memory module to ec/common/Scott2016-05-264-1/+398
| | | | | | | | | | | | | | | | | | | | | | | | Full implementation of NvMem read, write, and commit functions. Includes partition definitions, shared memory allocation, and initialization function. Includes a set of unit tests located in ec/test/nvmem.c which verify functionality. This module is required by Cr50, however this CL does not include any Cr50 specific code. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass Change-Id: I515b094f2179dbcb75dd11ab5b14434caad37edd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345632 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: increment prime generation counternagendra modadugu2016-05-261-6/+10
| | | | | | | | | | | | | | | | | | The counter used for prime generation should be incremented after each success / failure. Not doing so results in duplicate primes being picked when a label is explicitly specified. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: Ib2fd0e7fa6255b04946e6d2808e8c67a2199fb55 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/346056 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Driver: BD99955: Enable BC1.2 supportVijay Hiremath2016-05-242-2/+2
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=Manually tested on Amenia. Connected Zinger, Type-C, DCP & CDP chargers. Device can negotiate to desired current & voltage and the battery can charge. USB2.0 sync device is detected by Kernel. Change-Id: I58cb69289eef9a966e06bef8fe31d35beaec5e27 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341030 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: lars / kunimitsu (and _pd): Remove board-level codeShawn Nematbakhsh2016-05-121-4/+0
| | | | | | | | | | | | | | | | Authoritative firmware for these boards can be found on firmware-glados-7820.B branch. BUG=chrome-os-partner:49909 BRANCH=None TEST=`make buildall -j` Change-Id: I78dddef7bc36ecceb5cd9f0eb07052e8e16b6c15 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Allow TEST_LIST_HOST= to override test targetsBill Richardson2016-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When developing or tweaking tests, we almost always need to hack the Makefiles so that "make runtests" doesn't run *EVERY* test each time, but only the one we're playing with. This CL just allows you to override the default test_list_host values from the commandline. Of course, you shouldn't do this except when testing the tests themselves. BUG=none BRANCH=none TEST=manual # build all boards and run all tests make buildall -j14 # run all tests make runtests # run only the two specified tests TEST_LIST_HOST="lightbar hooks" make runtests Change-Id: Icd82c2c781a71a461a7d75bc4bd54944b0eaeed6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343003 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add support for RSA key generationnagendra modadugu2016-04-202-2/+515
| | | | | | | | | | | | | | | | | Prime generation uses a sieve to amortize division with small primes. Otherwise this a standard Miller-Rabin implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/335222 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: add support for P256-ECIES (hybrid encryption)nagendra modadugu2016-04-193-0/+236
| | | | | | | | | | | | | | | | | | Add support for P256 based hybrid encryption, and corresponding tests. Where hybrid encryption is: P256 based DH + AES128 + HMAC-SHA256. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 CQ-DEPEND=CL:336091,CL:339561 TEST=ECIES tests in test/tpm/tpmtest.py pass Change-Id: Ie091e278df72185a6896af0e498925e56404f87e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/337340 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: add support for RSA key "testing"nagendra modadugu2016-04-191-1/+28
| | | | | | | | | | | | | | | | | | | | | | Implement _cpri__TestKeyRSA, which computes the modulus and private exponent given a pair of primes, or computes the second prime and private exponent given the modulus and one prime. The _cpri__TestKeyRSA call is used to determine whether the components of an RSA key match each other. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/330466 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-7/+11
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add support for HKDF (RFC 5869)nagendra modadugu2016-04-143-0/+115
| | | | | | | | | | | | | | | | | Add support for SHA256 based HKDF key derivation as specified in RFC 5869. This change includes test vectors from the RFC. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/336091 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* tpmtest: support FTDI SPI on UltraDebugVadim Bendebury2016-04-131-0/+1
| | | | | | | | | | | | | | | | | The new debug board presents itself as a yet another USB device, it uses interface 1 for SPI. Add it to the table of devices we try to use. BRANCH=none BUG=none TEST=./test/tpm_test/tpm_test.py now succeeds again. Change-Id: Id14f17de6eff081bebed49d22ddc4b19cd39c2b0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338862 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: SPI tests need to poke the target to wake it upBill Richardson2016-04-061-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the Cr50 is in deep sleep, it does a full warm boot when it sees the SPS_CS_L assert. The master doesn't wait for it to boot (because it doesn't know it has to) and starts clocking in data bits right away. The Cr50 can't set up the SPS controller quickly enough to capture those bits, so the first N bits/bytes are lost and the master keeps clocking, waiting for the SPI response which it will never get. To be certain that the Cr50 is awake, this CL causes the test (master) to assert SPS_CS_L briefly, then wait a little bit for the Cr50 to wake up from deep sleep (50ms should be plenty), and THEN it can send the rest of the SPI traffic. The Cr50 won't enter deep sleep until it's been at least a second since the last SPI activity, so we don't have to worry about it going to sleep between SPI commands as long as they're not terribly far apart. The kernel driver will have to implement this same hack too, since the SPI bus doesn't have a suspend/resume protocol like the USB does. We've known this for some time. It would be nice if this weren't needed, but it's a hardware constraint. BUG=chrome-os-partner:49955, chrome-os-partner:52019, b:28018682 BRANCH=none TEST=make buildall; test on Cr50 Ensure that the Cr50 invokes sleep or deep sleep when idle (refer to previous commit messages for the setup required), then cd test/tpm_test make ./tpmtest.py Before this CL, the test hung or failed because it couldn't get a quick response from the Cr50. With this CL, the Cr50 wakes up and the test passes. Change-Id: I581475726313981a780beaaa37638e9c3b9ebec5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336837 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* sensor: update sensor driver to use I2C port from motion_sensor_tKevin K Wong2016-03-311-0/+2
| | | | | | | | | | | | | this allow motion sensor devices to be locate on different I2C port BUG=none BRANCH=none TEST=make buildall Change-Id: Ia7ba2f5729ebb19561768ec87fdb267e79aafb6a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334269 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: add NULL padding support for RSA encrypt/decryptnagendra modadugu2016-03-311-1/+11
| | | | | | | | | | | | | | | | | NULL padding (aka vanilla RSA) support is required by the TPM2 test suite (referred to as TPM_ALG_NULL in the tpm2 source). BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328830 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: add support for RSA PKCS1-PSS paddingnagendra modadugu2016-03-301-1/+3
| | | | | | | | | | | | | | | Add support for PSS padding as per RFC 3447. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under tpm2 pass Change-Id: I14c58394f742daa5de4ec2fbeb7e7f14e54c9fcc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328778 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Support USB SETCFG/GETCFG control transfersBill Richardson2016-03-303-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds USB support to Set and Get the Device Configuration. These control transfers are standard device requests that need to be added in order to behave properly for USB suspend/resume (and in general). Before this CL, the Get command always failed and the Set command had no effect internally. With this CL it works. Note that this particular change only supports ONE configuration for the Cr50. If/when we add additional configuration descriptors, we'll need to update it again. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; manual tests on Cr50 This CL includes a test program. Connect the Cr50 to the build host, and use that program to read and change the configuration. cd test/usb_test make ./device_configuration ./device_configuration 0 ./device_configuration 1 ./device_configuration 2 You may need to use sudo if your device permissions aren't sufficient. Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335878 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: test: do not leave the bootsrtap pin in the wrong stateVadim Bendebury2016-02-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | It was observed that the b1 test board falls into bootstrap mode once the reset button is pressed after a firmware upgrade. The reason turns out to be that the wrong lead was considered to be the reset pin, the BIO4, responsible for bootstrapping, was used instead of the reset pin. Come to think of it, there is no need to reset the device each time the FTDI SPI interface is initialized. Let's just drive the bootsrtap pin to the correct level and not generate the reset pulse at all. BRANCH=none BUG=chrome-os-partner:37754 TEST=pressing the reset button on the b1 board now properly restarts the device. Change-Id: I123dad8043807c8ff01e12254f9efc2f0d1aaa13 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/328811 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: add firmware upgrade testVadim Bendebury2016-02-173-2/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the test harness with a test verifying firmware upgrade. The test in fact just determines the area available for upgrade, picks the appropriate image and sends it to the device, 1K at a time. The test does not verify that the device in fact switched to the new image, the test succeeds if the device accepts all update messages. BRANCH=none BUG=chrome-os-partner:37774 TEST=verified that all tests still pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 SUCCESS: EC-SIGN:NIST-P256:ECDSA New max timeout: 1 s SUCCESS: EC-KEYGEN:NIST-P256 SUCCESS: EC-KEYDERIVE:NIST-P256 SUCCESS: sha1:single:0 SUCCESS: sha256:single:0 SUCCESS: sha1:single:3 SUCCESS: sha256:single:3 SUCCESS: sha256:finish:1 SUCCESS: sha1:finish:3 SUCCESS: sha256:finish:2 -New max timeout: 3 s SUCCESS: RSA-ENC:OAEP:SHA1:768 SUCCESS: RSA-ENC:OAEP:SHA256:768 SUCCESS: RSA-ENC:PKCS1-ES:NONE:768 New max timeout: 49 s SUCCESS: RSA-ENC:PKCS1-ES:NONE:2048 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA1:768 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA256:768 SUCCESS: Firmware upgrade Change-Id: I49052feb8e97a3e281bb20b7fddc359a55e96ae3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327416 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: modify mpsse to work with the new deviceVadim Bendebury2016-02-132-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The ultra debug board uses a different FTDI chip (vid:did 0403:6010), which has two ports. The SPI interface on this chip is hooked up to the second port, but the code indiscriminately uses the first port when trying to open the SPI channel, on all devices known to it. Adding a new field in the supported_devices table allows to keep default behavior, but use port B (the second port) when required. Also, fix printout formatting problem. BRANCH=none BUG=chrome-os-partner:37754 TEST=tpmtest succeeds with the new board Change-Id: I01f7937444c8df61d7439a66d9da89fb2cac5372 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327232 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: test: consolidate test exceptionsVadim Bendebury2016-02-116-63/+53
| | | | | | | | | | | | | | | | | | | | | | There is no point in defining tpm test exception classes per test type, one common class is enough, especially if the source module of the exception is reported. BRANCH=none BUG=none TEST=tried running the test without the USB FTDI cable plugged in, got the following error message: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Error in tpmtest.py:54: Failed to connect $ Change-Id: I5642aa70c8a581099887b58e3a436d7f8d7608a1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327300 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: test: use gcc for linkingVadim Bendebury2016-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | For some reason the default linker does not find libftdi1 anymore. Other Chrome OS packages linking to this library still build just fine, it turns out they are using the default gcc for linking. Let's do the same for building tpmtest library. BRANCH=none BUG=none TEST=the following sequence now works fine: cd test/tmp_test touch * make and the resulting library allows to successfully run TPM tests on the b1 board. Change-Id: I10fe51a4747a3527b500d3255d8347e6a689c345 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327065 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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