summaryrefslogtreecommitdiff
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
* CR50: add tests for 1024-bit RSA.nagendra modadugu2016-06-011-6/+16
| | | | | | | | | | | | | | | | | | | | Add tests for RSA-1024, and created partner CRBUG/53893 to track issue discovered with 1024-bit modinv. 1024-bit RSA support being added in preparation for a forthcoming hardware based implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53893 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: I6b5aaeffc9df1cbbe403535fd21cdd377b42c38e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/348490 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: NvMem: Connected function stubs in /board/tpm2/NVMem.cScott2016-05-261-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | | Used #define CONFIG_FLASH_NVMEM to have functions in /board/tpm2/NVMem.c utlitize on chip Nvmem functions. On chip NV Memory availability is tied to an internal nvmem error state which itself only depends on finding at least one valid partition. Added nvmem_is_different and nvmem_move functions which were needed to complete the tpm2 platform interface. In addition, added unit tests to support these two new functions. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass. Tested with tcg_test utility to test reads/writes using the command "build/test-tpm2/install/bin/compliance --ntpm localhost:9883 --select CPCTPM_TC2_3_33_07_01". Change-Id: I475fdd1331e28ede00f9b674c7bee1536fa9ea48 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/346236 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* NvMem: Added NV Memory module to ec/common/Scott2016-05-264-1/+398
| | | | | | | | | | | | | | | | | | | | | | | | Full implementation of NvMem read, write, and commit functions. Includes partition definitions, shared memory allocation, and initialization function. Includes a set of unit tests located in ec/test/nvmem.c which verify functionality. This module is required by Cr50, however this CL does not include any Cr50 specific code. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual make runtests TEST_LIST_HOST=nvmem and verify that all tests pass Change-Id: I515b094f2179dbcb75dd11ab5b14434caad37edd Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345632 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: increment prime generation counternagendra modadugu2016-05-261-6/+10
| | | | | | | | | | | | | | | | | | The counter used for prime generation should be incremented after each success / failure. Not doing so results in duplicate primes being picked when a label is explicitly specified. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=all tests in test/tpm_test/tpmtest.py pass Change-Id: Ib2fd0e7fa6255b04946e6d2808e8c67a2199fb55 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/346056 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Driver: BD99955: Enable BC1.2 supportVijay Hiremath2016-05-242-2/+2
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=Manually tested on Amenia. Connected Zinger, Type-C, DCP & CDP chargers. Device can negotiate to desired current & voltage and the battery can charge. USB2.0 sync device is detected by Kernel. Change-Id: I58cb69289eef9a966e06bef8fe31d35beaec5e27 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341030 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: lars / kunimitsu (and _pd): Remove board-level codeShawn Nematbakhsh2016-05-121-4/+0
| | | | | | | | | | | | | | | | Authoritative firmware for these boards can be found on firmware-glados-7820.B branch. BUG=chrome-os-partner:49909 BRANCH=None TEST=`make buildall -j` Change-Id: I78dddef7bc36ecceb5cd9f0eb07052e8e16b6c15 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Allow TEST_LIST_HOST= to override test targetsBill Richardson2016-05-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When developing or tweaking tests, we almost always need to hack the Makefiles so that "make runtests" doesn't run *EVERY* test each time, but only the one we're playing with. This CL just allows you to override the default test_list_host values from the commandline. Of course, you shouldn't do this except when testing the tests themselves. BUG=none BRANCH=none TEST=manual # build all boards and run all tests make buildall -j14 # run all tests make runtests # run only the two specified tests TEST_LIST_HOST="lightbar hooks" make runtests Change-Id: Icd82c2c781a71a461a7d75bc4bd54944b0eaeed6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343003 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add support for RSA key generationnagendra modadugu2016-04-202-2/+515
| | | | | | | | | | | | | | | | | Prime generation uses a sieve to amortize division with small primes. Otherwise this a standard Miller-Rabin implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/335222 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: add support for P256-ECIES (hybrid encryption)nagendra modadugu2016-04-193-0/+236
| | | | | | | | | | | | | | | | | | Add support for P256 based hybrid encryption, and corresponding tests. Where hybrid encryption is: P256 based DH + AES128 + HMAC-SHA256. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 CQ-DEPEND=CL:336091,CL:339561 TEST=ECIES tests in test/tpm/tpmtest.py pass Change-Id: Ie091e278df72185a6896af0e498925e56404f87e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/337340 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: add support for RSA key "testing"nagendra modadugu2016-04-191-1/+28
| | | | | | | | | | | | | | | | | | | | | | Implement _cpri__TestKeyRSA, which computes the modulus and private exponent given a pair of primes, or computes the second prime and private exponent given the modulus and one prime. The _cpri__TestKeyRSA call is used to determine whether the components of an RSA key match each other. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/330466 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-7/+11
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: add support for HKDF (RFC 5869)nagendra modadugu2016-04-143-0/+115
| | | | | | | | | | | | | | | | | Add support for SHA256 based HKDF key derivation as specified in RFC 5869. This change includes test vectors from the RFC. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/336091 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* tpmtest: support FTDI SPI on UltraDebugVadim Bendebury2016-04-131-0/+1
| | | | | | | | | | | | | | | | | The new debug board presents itself as a yet another USB device, it uses interface 1 for SPI. Add it to the table of devices we try to use. BRANCH=none BUG=none TEST=./test/tpm_test/tpm_test.py now succeeds again. Change-Id: Id14f17de6eff081bebed49d22ddc4b19cd39c2b0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338862 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: SPI tests need to poke the target to wake it upBill Richardson2016-04-061-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the Cr50 is in deep sleep, it does a full warm boot when it sees the SPS_CS_L assert. The master doesn't wait for it to boot (because it doesn't know it has to) and starts clocking in data bits right away. The Cr50 can't set up the SPS controller quickly enough to capture those bits, so the first N bits/bytes are lost and the master keeps clocking, waiting for the SPI response which it will never get. To be certain that the Cr50 is awake, this CL causes the test (master) to assert SPS_CS_L briefly, then wait a little bit for the Cr50 to wake up from deep sleep (50ms should be plenty), and THEN it can send the rest of the SPI traffic. The Cr50 won't enter deep sleep until it's been at least a second since the last SPI activity, so we don't have to worry about it going to sleep between SPI commands as long as they're not terribly far apart. The kernel driver will have to implement this same hack too, since the SPI bus doesn't have a suspend/resume protocol like the USB does. We've known this for some time. It would be nice if this weren't needed, but it's a hardware constraint. BUG=chrome-os-partner:49955, chrome-os-partner:52019, b:28018682 BRANCH=none TEST=make buildall; test on Cr50 Ensure that the Cr50 invokes sleep or deep sleep when idle (refer to previous commit messages for the setup required), then cd test/tpm_test make ./tpmtest.py Before this CL, the test hung or failed because it couldn't get a quick response from the Cr50. With this CL, the Cr50 wakes up and the test passes. Change-Id: I581475726313981a780beaaa37638e9c3b9ebec5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336837 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* sensor: update sensor driver to use I2C port from motion_sensor_tKevin K Wong2016-03-311-0/+2
| | | | | | | | | | | | | this allow motion sensor devices to be locate on different I2C port BUG=none BRANCH=none TEST=make buildall Change-Id: Ia7ba2f5729ebb19561768ec87fdb267e79aafb6a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334269 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: add NULL padding support for RSA encrypt/decryptnagendra modadugu2016-03-311-1/+11
| | | | | | | | | | | | | | | | | NULL padding (aka vanilla RSA) support is required by the TPM2 test suite (referred to as TPM_ALG_NULL in the tpm2 source). BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328830 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: add support for RSA PKCS1-PSS paddingnagendra modadugu2016-03-301-1/+3
| | | | | | | | | | | | | | | Add support for PSS padding as per RFC 3447. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under tpm2 pass Change-Id: I14c58394f742daa5de4ec2fbeb7e7f14e54c9fcc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328778 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Support USB SETCFG/GETCFG control transfersBill Richardson2016-03-303-0/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds USB support to Set and Get the Device Configuration. These control transfers are standard device requests that need to be added in order to behave properly for USB suspend/resume (and in general). Before this CL, the Get command always failed and the Set command had no effect internally. With this CL it works. Note that this particular change only supports ONE configuration for the Cr50. If/when we add additional configuration descriptors, we'll need to update it again. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; manual tests on Cr50 This CL includes a test program. Connect the Cr50 to the build host, and use that program to read and change the configuration. cd test/usb_test make ./device_configuration ./device_configuration 0 ./device_configuration 1 ./device_configuration 2 You may need to use sudo if your device permissions aren't sufficient. Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335878 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* cr50: test: do not leave the bootsrtap pin in the wrong stateVadim Bendebury2016-02-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | It was observed that the b1 test board falls into bootstrap mode once the reset button is pressed after a firmware upgrade. The reason turns out to be that the wrong lead was considered to be the reset pin, the BIO4, responsible for bootstrapping, was used instead of the reset pin. Come to think of it, there is no need to reset the device each time the FTDI SPI interface is initialized. Let's just drive the bootsrtap pin to the correct level and not generate the reset pulse at all. BRANCH=none BUG=chrome-os-partner:37754 TEST=pressing the reset button on the b1 board now properly restarts the device. Change-Id: I123dad8043807c8ff01e12254f9efc2f0d1aaa13 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/328811 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: add firmware upgrade testVadim Bendebury2016-02-173-2/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extends the test harness with a test verifying firmware upgrade. The test in fact just determines the area available for upgrade, picks the appropriate image and sends it to the device, 1K at a time. The test does not verify that the device in fact switched to the new image, the test succeeds if the device accepts all update messages. BRANCH=none BUG=chrome-os-partner:37774 TEST=verified that all tests still pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 SUCCESS: EC-SIGN:NIST-P256:ECDSA New max timeout: 1 s SUCCESS: EC-KEYGEN:NIST-P256 SUCCESS: EC-KEYDERIVE:NIST-P256 SUCCESS: sha1:single:0 SUCCESS: sha256:single:0 SUCCESS: sha1:single:3 SUCCESS: sha256:single:3 SUCCESS: sha256:finish:1 SUCCESS: sha1:finish:3 SUCCESS: sha256:finish:2 -New max timeout: 3 s SUCCESS: RSA-ENC:OAEP:SHA1:768 SUCCESS: RSA-ENC:OAEP:SHA256:768 SUCCESS: RSA-ENC:PKCS1-ES:NONE:768 New max timeout: 49 s SUCCESS: RSA-ENC:PKCS1-ES:NONE:2048 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA1:768 SUCCESS: RSA-SIGN:PKCS1-SSA:SHA256:768 SUCCESS: Firmware upgrade Change-Id: I49052feb8e97a3e281bb20b7fddc359a55e96ae3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327416 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: modify mpsse to work with the new deviceVadim Bendebury2016-02-132-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The ultra debug board uses a different FTDI chip (vid:did 0403:6010), which has two ports. The SPI interface on this chip is hooked up to the second port, but the code indiscriminately uses the first port when trying to open the SPI channel, on all devices known to it. Adding a new field in the supported_devices table allows to keep default behavior, but use port B (the second port) when required. Also, fix printout formatting problem. BRANCH=none BUG=chrome-os-partner:37754 TEST=tpmtest succeeds with the new board Change-Id: I01f7937444c8df61d7439a66d9da89fb2cac5372 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327232 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: test: consolidate test exceptionsVadim Bendebury2016-02-116-63/+53
| | | | | | | | | | | | | | | | | | | | | | There is no point in defining tpm test exception classes per test type, one common class is enough, especially if the source module of the exception is reported. BRANCH=none BUG=none TEST=tried running the test without the USB FTDI cable plugged in, got the following error message: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Error in tpmtest.py:54: Failed to connect $ Change-Id: I5642aa70c8a581099887b58e3a436d7f8d7608a1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327300 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: test: use gcc for linkingVadim Bendebury2016-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | For some reason the default linker does not find libftdi1 anymore. Other Chrome OS packages linking to this library still build just fine, it turns out they are using the default gcc for linking. Let's do the same for building tpmtest library. BRANCH=none BUG=none TEST=the following sequence now works fine: cd test/tmp_test touch * make and the resulting library allows to successfully run TPM tests on the b1 board. Change-Id: I10fe51a4747a3527b500d3255d8347e6a689c345 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327065 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* CR50: Add initial elliptic curve crypto implementation.nagendra modadugu2016-02-083-0/+172
| | | | | | | | | | | | | | | | This change adds support for NIST-P256 curve operations. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=new tests under test/tpm2/ pass. Change-Id: I03a35ff3ab8af3c52282d882937880bfa2bdcd32 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324540 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Fix bug in software sha256_hash()nagendra modadugu2016-01-281-0/+2
| | | | | | | | | | | | | | | | | The implementation for sha256_hash() copied and incorrect number of bytes to the output. This change provides a fix and a test. TEST=added test case BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I74e98c6f5005a14dd5c0ca19ea7540622dd6c7d7 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324391 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* test/flash: Use signal enum instead of string nameAnton Staaf2016-01-191-5/+6
| | | | | | | | | | | | | | | | | | Previously the flash test used the GPIO string name to identify the write protect GPIO. Change to use the GPIO signal enum. This is faster and removes a use of gpio_list. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I4203c33cfa6d2b25d73d886b5248857a0c271565 Reviewed-on: https://chromium-review.googlesource.com/321913 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Initial RSA implementation.stabilize-7821.Bnagendra modadugu2016-01-113-2/+177
| | | | | | | | | | | | | | | | | | | | | Includes support for encrypt / decrypt, and sign / verify; padding schemes OAEP / PKCS1; supporting bignum library. RSA key sizes must be a multiple of 32-bits (with the top bit set). Keying material, input and output buffers are required to be word-aligned. BRANCH=none TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/316942 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* pd: Add common EC_HOST_EVENT_PD_MCU implementationShawn Nematbakhsh2016-01-073-9/+5
| | | | | | | | | | | | | | | | | | | | | For TCPMs with an off chip TCPC, PD MCU host event status can be handled in a common way. When a status flag is updated (ex. from charge_manager), notify the AP through the host event, and save the status flag for later retrieval. BUG=chrome-os-partner:49124 BRANCH=None TEST=Verify `cat /sys/class/power_supply/CROS_USB_PD_CHARGER1/online` on chell reflects the actual online status of the charger. Also verify UI charge icon tracks the online status correctly. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I63bc70205627474590e38ffd282faedaea3bcc66 Reviewed-on: https://chromium-review.googlesource.com/320796 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Refactor crypto subcommands into their own python module.nagendra modadugu2015-12-173-7/+14
| | | | | | | | | | | | | BRANCH=none TEST=tpmtest.py passes BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: I48f426176f17c57c723104d19c963b228f16d985 Reviewed-on: https://chromium-review.googlesource.com/318915 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: test: add hash testing host side implementationVadim Bendebury2015-12-032-1/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new module generates hash test extension subcommands, driven by the 'test_inputs' table. Each table entry is a tuple, including the test name and the data to be hashed. The test name determines the hash type (sha1 or sha256) and the test mode (single or spread over several messages). The last element of the name is the context number (ignored in single message mode). The hash extended command payload looks as follows: field | size | note =================================================================== hash_cmd | 1 | 0 - start, 1 - cont., 2 - finish, 4 - single hash_mode | 1 | 0 - sha1, 1 - sha256 handle | 1 | session handle, ignored in 'single' mode text_len | 2 | size of the text to process, big endian text | text_len | text to hash BRANCH=none BUG=chrome-os-partner:43025 TEST=currently failing, a couple of hash code tweaks needed, see upcoming patches. Change-Id: Ie992bf01cae3c5278110357b482370b2fc11c70f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314693 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: test: move crypto test into its own moduleVadim Bendebury2015-12-033-230/+267
| | | | | | | | | | | | | | | | | | | | | | | | This is a no-op change moving some common code out of tpmtest.py, preparing it to support different testing modes. BRANCH=none BUG=chrome-os-partner:43025 TEST=the AES test still succeeds: $ test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 Change-Id: Ia6e0e3e89f99875297da0a4f6137de5901c8ca08 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314691 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: test: extended command code does not have to be passed as argumentVadim Bendebury2015-12-011-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The extended command code is fixed, there is no need to pass it as a parameter when calling functions wrapping and unwrapping extended commands. BRANCH=none BUG=chrome-os-partner:43025 TEST=AES tests still pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 -New max timeout: 1 s SUCCESS: AES:CTR256I 1 Change-Id: Ic0c9d7983755de8380b57e841891fd638ef2c62a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314690 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: Extended command test utilityVadim Bendebury2015-11-2110-0/+2128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The utility builds on the extended command protocol recently introduced in the EC and allows to test implementation of various cryptographic primitives available on CR50. This patch brings in the ftdi_spi_tpm.c and mpsse.c from the AOSP trunksd package. mpsse.c has been modified to limit its feature set (no i2c or bigbang support, only SPI0 mode), and ftdit_spi_tpm.c has been modified to properly present binary strings to the Python swig wrapper. The crypro_test.xml file includes descriptions of the tests to perform on the target. Most of its contents other than the first crypto_test element are borrowed from NIST AES test vectors set. See file header for description of the contents format. The actual test command is the tpmtest.py. When started it establishes connection with the device, and then reads test vectors from crypto_test.xml and executes them one at a time. Starting the test program with the -d command line argument enables debug output sent to the console. There are some other programs in ./extras which use the mpsse.c from AOSP, they will have to be modified to use the local copy. BRANCH=none BUG=chrome-os-partner:43025 TEST=ran the following in the directory: $ make # output suppressed $ ./tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 \New max timeout: 1 s SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 - temporarily corrupted the contents of the clear_text element of 'AES:ECB common': $ ./tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 | Out text mismatch in node AES:ECB common, operation 1: In text: 74 68 69 73 20 20 69 73 20 74 68 65 20 74 65 78 74 20 77 68 69 63 68 20 77 69 6c 6c 20 62 65 20 65 6e 63 72 79 70 74 65 64 20 69 66 20 65 76 65 72 79 74 68 69 6e 67 20 69 73 20 67 6f 69 6e 67 20 66 69 6e 65 2e 20 Expected out text: 3d e2 0f f9 ee d9 62 ce f0 8a 17 57 c6 04 86 d0 3d ec 44 72 d8 79 18 87 3f 31 81 6d 66 4c bb 10 da 8d e0 9f 63 67 b3 cc 64 b4 e8 bd 12 b0 a9 c9 09 6d f0 9f a4 e2 ae fb 0d fe 1c 90 6c e2 fe f0 68 8f b5 34 07 76 e2 a9 72 8e dd 7b 8b 52 2b 8b Real out text: f9 50 fe 93 c9 3f cb e5 9e e0 a4 7e 51 1a bb a0 36 2f d1 d6 5f a8 1d 22 5a 1a bb f7 e6 65 89 55 ad e8 f5 8f 1a 20 ff a5 c4 de 76 3e b8 ef cc 8d 9d 94 b8 89 22 1c c9 2a 43 58 c3 8c 75 9f 9f 56 ab 2f 89 1a f6 a0 36 8b 95 23 91 d6 23 47 77 36 Change-Id: I2687ac03236b528e71b92df7cb35606e473ab2c5 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313443 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* motion: Change units of ec_rate from us to ms.Gwendal Grignou2015-11-181-4/+4
| | | | | | | | | | | | | To ease finer calculation of ec rate change units from ms to us. BRANCH=smaug BUG=b:24367625 TEST=compile Change-Id: I52057c8ca1b1180a64b58d1ba0af9ec53f40b026 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312984
* motion: cleanup include fileGwendal Grignou2015-11-121-0/+2
| | | | | | | | | | | | | | Use test_export_static for static variable/function that needs to by used by tests/motion_lid.c BRANCH=smaug BUG=none TEST=Compile, make buildall -j Change-Id: I2f3eb72ce319622842885be9125b91e58f47133a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311754 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-032-2/+7
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* glados: oak: chell: enable USB PD loggingAlec Berg2015-10-301-0/+2
| | | | | | | | | | | | | | | Enable USB PD logging. BUG=chrome-os-partner:45933 BRANCH=none TEST=make -j buildall make -j BOARD=glados tests Load on glados and test that PDLOG events show up in dmesg Change-Id: I61dbc5019ea3228542c2c244228bbb483cf51ead Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309881 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* motion: Remove duplicate shutdown codeGwendal Grignou2015-10-281-1/+3
| | | | | | | | | | | | | | | | | Call shutdown() entry point at init() and remove duplicate code. shutdown would init the sensor so they would be ready if needed. Set S5 flag to include G3 (hard off) state, not only S5 (soft off). BUG=chrome-os-partner:45722 BRANCH=smaug TEST=When doing a RO->RW transition while AP is in G3, check the sensors are initialized properly. This issue was found while testng the magic sequence code. Change-Id: I647f83580240bf5ba0c340fca3184220abe4c12e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308561 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* charger: Add LIMIT_POWER charger param for low bat + weak chargerShawn Nematbakhsh2015-10-271-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for two new configs to specify critical energy battery percentage and critical external charger power. When we are under both thresholds, set the LIMIT_POWER charger parameter to inform the AP that it should conserve power to avoid brownout, and consider jumping to EC RW to negotiate PD. In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON to allow power-up regardless of power level if a 15W+ charger is attached, since there is a reasonable chance it may speak PD and provide sufficient power to boot the AP. BUG=chromium:537269 TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also veify that system can boot with Donette. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad Reviewed-on: https://chromium-review.googlesource.com/306774 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* common: lightbar: Add histeresis to prevent flickeringGwendal Grignou2015-10-232-0/+50
| | | | | | | | | | | | | | | | | | | | | | | When ALS is enabled, if light is around one threshold (say 40 lux), the lightbar will flicker between readings. Add a histeresis to prevent the flickering. The current setting is: setting ^ (dim) 2 | ------+---->---+ 1 | +----<---+--->---+ (bright) 0 | +---<---+--------- +-------+--------+-------+--------> lux 20 40 60 BRANCH=smaug BUG=chrome-os-partner:44400 TEST=check in a dark room (30~40 lux) there is no flickering. Add unit test. Change-Id: I4018e2c2ed764abf9c9ed28e2d50a3e94a7d5f75 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308205
* Lars: Init boardRyan Zhang2015-10-221-0/+1
| | | | | | | | | | | | | | | | | Preparing for new board, Lars Copy kunimitsu setting to init board. BUG=none BRANCH=lars TEST=Run "make -j BOARD=lars", "make -j BOARD=lars_pd" and "make buildall -j" to build code and ec.bin can be generated. Change-Id: Ic0ab3e57679fc7ea98a7b73527ce2276e706db1d Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/305128 Commit-Ready: 志偉 黃 <David.Huang@quantatw.com> Tested-by: 志偉 黃 <David.Huang@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados_pd: oak_pd: add and enable option for i2c slave onlyAlec Berg2015-10-191-2/+2
| | | | | | | | | | | | | | Add CONFIG_I2C_SLAVE_ONLY for boards that only operate as a slave on i2c. BUG=chrome-os-partner:41959 BRANCH=none TEST=make BOARD=glados_pd and see 2kB flash savings Change-Id: I30831ce48b391d985c25e266229d5c6f2312042b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306783 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chell: Add EC/PD configuration for chell boardDuncan Laurie2015-10-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add new EC board for chell proto: - no motion sensors or tablet mode - no independent volume buttons - no ALS - 2x PS8740 USB MUX - apply PMIC_LDO_EN behavior by default - leave SLP_S0 workaround in place until HW is updated - misc GPIO changes - update battery info with basic 3S config from blaze - remove custom battery charger profile The PD board is a symlink to glados as it appears to be the same. BUG=chrome-os-partner:46289 BRANCH=none TEST=make -j BOARD=chell ; make -j BOARD=chell_pd Change-Id: I1084d663b06eeb55f035b10eb776a2e30e0f7074 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/304398 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* test: motion_lid: reenableGwendal Grignou2015-09-291-1/+1
| | | | | | | | | | | | | | After fixes CL:300630, motion_lid test is fixed: motion_sense task was exiting during the tests. BRANCH=smaug BUG=chrome-os-partner:42855 TEST=motion_lid test now pass. Change-Id: I7bc464fb2766684093de9b3e479fb5ac3718df04 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302861 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* common: motion: Separate motion task interval from AP configurationGwendal Grignou2015-09-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | Some sensors are in forced mode, motion sense must be scheduled at their ODR. However the host may not want the data right away, so motion task may not wake up the host that often. Add a new variable motion_int_interval that defines the maximum interval between FIFO host event. BRANCH=smaug BUG=chrome-os-partner:43800 TEST=Check that light sensor is polled at ODR frequency. Check that when AP does not want any event, no FIFO host event are requested. Check CTS tests work as before. Reenable motion_lid unit test. Change-Id: Ie25e6cbe28fed899073856057855ffa03c0cd9fd Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301134 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* motion: add config option to use the old accelerometer ref frameAlec Berg2015-09-172-2/+3
| | | | | | | | | | | | | | | | | | | | | | | Add config option to use the old accelerometer reference frame, which is used on samus and products using 3.14 or earlier kernel. This fixes samus so that the lid angle calculation is correct again. This also moves the accel_orientation structure out of the board directory and into common code, since it purely is a function of the reference frame being used. BUG=chrome-os-partner:43494 BRANCH=none TEST=test on samus, verify lid angle calculation is correct once again. also, enable the motion_lid test and verify that it passes. Change-Id: I948a74a71964b54c68be66e828a030ddd0418947 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/300510 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* host: mock i2c_xferGwendal Grignou2015-09-161-11/+16
| | | | | | | | | | | | | | | Instead of mocking i2c_read8/16/32, mock i2c_xfer. We can now test code that call i2c_xfer directly and test common/i2c.c BRANCH=samus, ryu BUG=chrome-os-partner:45223 TEST=Unit tests pass. Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299768 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Change meaning of storage offset CONFIGsShawn Nematbakhsh2015-09-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | In order to support architectures with non-contiguous writable and protected regions, change storage offsets to be relative to writable and protected regions, rather than relative to "the start of the region of storage belonging to the EC". Spec doc available at https://goo.gl/fnzTvr. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4 Reviewed-on: https://chromium-review.googlesource.com/297823 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* temp_sensor: Separate ADC interface and thermistor mathsWonjoon Lee2015-09-112-8/+8
| | | | | | | | | | | | | | | | | | Separate the bd99992gw ADC interface from the NCP15WB thermistor adc-to-temp maths so that the thermistor can be used with various other interfaces. BUG=chrome-os-partner:44764 TEST=make buildall -j Manual on Glados. Boot to S0, run "temps". Verify that temperatures start around 28C and begin to increase after system is powered-on for a long duration. BRANCH=None Change-Id: I3e72e9f390feebaac2440dbe722485f8d1cf8c56 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/296871 Reviewed-by: Shawn N <shawnn@chromium.org>
View Lorry Controller Status