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* cr50: signer: sync up with upstreamVadim Bendebury2016-02-271-0/+7
| | | | | | | | | | | | | | | This change just copies files shared between two repositories which have changed since the last sync up. This time it is as of @CL85098. BRANCH=none BUG=none TEST=the signed image boots fine on the b1 board. Change-Id: I7a1d1b344119e6f6729a38bbea04da75f2d3371c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329407 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: signer: pick up latest and greatestVadim Bendebury2016-02-081-0/+3
| | | | | | | | | | | | | | These are relevant changes in the FPGA tree since the most recent sync up. BRANCH=none BUG=chrome-os-partner:50141 TEST=image signed by the new signer boots successfully. Change-Id: Id30c5da614aa5c2496305f9687bce06030449beb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326483 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: util: signer: make signer header definition usable on the targetVadim Bendebury2015-11-101-4/+0
| | | | | | | | | | | | | | | | | | | | The signer running on the build host and the loader running on the target must be in sync as of the structure of the signature header. To be able to use the same definition in both programs, remove the system includes from the .h file which needs to be shared. Rearrange includes in image.cc to follow the coding conventions. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applied the code successfully boots, which indicates that the signer is in fact working properly. (See the top patch for testing details). Change-Id: I6bc9c57ebea55ac256fcdac8338c5566f16b6371 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311420 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Update to the "final" FPGA image 20151104_041733@78962Bill Richardson2015-11-062-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In fact this provides support for three FPGA images: 20151104_011218 - full crypto, no USB 20151104_041733 - tiny crypto, full USB 20151104_065845 - full crypto, full USB (only for hard-to-get boards) We can tell these FPGA images apart at run-time by looking at some SWDP registers: register crypto usb full GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135 GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3 This CL includes a run-time check for the USB features so that it's safe to build the firmware with CONFIG_USB and run it on a non-USB FPGA image. Here are the differences I could find in the top-level image header files: All three FPGA images define different (apparently arbitrary) default values for the PMU_PWRDN_SCRATCHn registers, but other than that, the usb and full images differ only in the BUILD_TIME and FPGA_CONFIG register values. I'm not sure why, but function uart_init() in file chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn registers, but nothing seems to read it again. The crypto image defines these values which don't appear in the other images: #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52 #define PINMUX_USB0_EXT_RX_DMI_SEL 0x53 #define PINMUX_USB0_EXT_RX_DPI_SEL 0x54 #define PINMUX_USB0_EXT_RX_RCV_SEL 0x55 #define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56 #define PINMUX_USB0_EXT_TX_DMO_SEL 0x57 #define PINMUX_USB0_EXT_TX_DPO_SEL 0x58 #define PINMUX_USB0_EXT_TX_OEB_SEL 0x59 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240 #define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244 #define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248 #define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c #define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250 #define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254 #define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258 #define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 The crypto image also differs in this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c instead of this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230 The rest of the differences between the crypto and usb versions are in these values, which I don't think we care about. At least, I can't find any place where they're used. PINMUX_EXITEDGE0_DIOAn_OFFSET PINMUX_EXITEDGE0_DIOBn_OFFSET PINMUX_EXITEDGE0_DIOMn_OFFSET PINMUX_EXITEDGE0_VIOn_OFFSET PINMUX_EXITEDGE0_OFFSET PINMUX_EXITEN0_DIOAn_OFFSET PINMUX_EXITEN0_DIOBn_OFFSET PINMUX_EXITEN0_DIOMn_OFFSET PINMUX_EXITEN0_VIOn_OFFSET PINMUX_EXITEN0_OFFSET PINMUX_EXITINV0_DIOAn_OFFSET PINMUX_EXITINV0_DIOBn_OFFSET PINMUX_EXITINV0_DIOMn_OFFSET PINMUX_EXITINV0_VIOn_OFFSET PINMUX_EXITINV0_OFFSET PINMUX_HOLD_OFFSET PINMUX_SEL_COUNT PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET PINMUX_XO0_TESTBUSn_SEL PINMUX_XO0_TESTBUSn_SEL_OFFSET I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h BRANCH=none BUG=chrome-os-partner:43791 CQ-DEPEND=CL:310978 TEST=make buildall I also built a single Cr50 firmware and tried it on both the crypto and usb FPGA images. Both worked as expected. Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311211
* Cr50: Support FPGA image m3.dist_20151021_054409Bill Richardson2015-10-224-17/+42
| | | | | | | | | | | | | | | | This enables support for a new FPGA image with tighter timing constraints. Some USB functions perform better using this model. There are also changes to the signing code. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall Change-Id: I608c2424d76b4ea566bf56fa0fed3810436216bb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308063 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: upgrade to the latest FPGA image (20151012_041715@75660)Vadim Bendebury2015-10-123-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the suggested USB build. The spiflash utility must come from the same tarball. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: boot_rom 20151012_041715@75660 - booted the new image using the latest spiflash version. Note that the bootrom now reports the FPGA image it comes from - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11 > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I4e21151d03d1050999ea2045b2be4b99886ff15c Reviewed-on: https://chromium-review.googlesource.com/305260 Commit-Ready: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: upgrade to the latest FPGA image (20151007_064811)Vadim Bendebury2015-10-072-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the suggested USB build. The spiflash utility must come from the same tarball. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: BootRom 0.8.91hw - booted the new image using the latest spiflash version. Note that the bootrom now reports the FPGA image it comes from: BootRom 20151007_064811@75052 - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11 > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iccd8f202493951f803393395273caa83467655df Reviewed-on: https://chromium-review.googlesource.com/304622 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: upgrade to the latest FPGA imageVadim Bendebury2015-10-052-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the suggested USB build (20151005_041713). The spiflash utility must come from the same tarball. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: BootRom 0.8.91hw - booted the new image using the latest spiflash version. - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11 > Change-Id: Iff778087149ae3e7570f8fd4d81c2857a4ea5367 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/304123 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: upgrade signer to latest and greatestVadim Bendebury2015-09-296-0/+255
This patch brings in the enhanced signer utility published along with FPGA version 20150925_21715, and the image.cc file updated to fix the bug where it was not picking up the initialized data segment from the elf file. The new signed image header format, among other things, describes memory areas as read-only and read-execute, which allows the bootrom to configure the MMU appropriately. Makefiles had to be modified to reflect the fact that the signed image now depends on .elf, not on .raw, and that building the signer requires more source files. Note that some signer features are not yet being utilized (like processing xml files describing fuses or retrieving keys from gnubby), the source are kept for completeness. BRANCH=none BUG=chrome-os-partner:43791 TEST=build the cr50 image and boot in on the FPGA board using the spiflash utility outside chroot. Observe the target starting the console session. Change-Id: Ib59b8ebbeb98a8146d4d997e1f78178c4fbc031a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/303070 Commit-Ready: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
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