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* zephyr: NPCX EVB: disable unused I2C controllersKeith Short2021-09-271-0/+20
| | | | | | | | | | | | | | | Upstream Zephyr now requires that both the I2C port and I2C controller are explicitly enabled. BUG=b:200292035 BRANCH=none TEST=zmake testall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I32cae81567fc9420c293e06128653039a69f6d75 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3188562 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* zephyr: drivers: thermistors are device tree nodesAaron Massey2021-09-241-4/+13
| | | | | | | | | | | | | | | | | | | Thermistor drivers now query the device tree for configuration. Thermistor tests have been updated to be parameterized on all thermistors enabled in the device tree. BRANCH=none BUG=b:184374937 TEST= 1) zmake testall 2) make runhosttests Cq-Depend: chromium:3161332 Signed-off-by: Aaron Massey <aaronmassey@chromium.org> Change-Id: Ic5330cd5c33e79e192428ca857651de9a225856e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133812 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Aaron Massey <aaronmassey@google.com> Commit-Queue: Aaron Massey <aaronmassey@google.com>
* zephyr: guybrush: enable I2C controllersKeith Short2021-09-231-0/+32
| | | | | | | | | | | | | | | Explicitly enable all used I2C controllers. CL:3176841 disables the NPCX I2C controllers by default to save flash and RAM space. BUG=b:200292035 BRANCH=none TEST=zmake testall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If2bbfbaee2e8392040776a9c87f0464274a7f2dd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3177580 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Explicitly enable the I2C controllerKeith Short2021-09-204-0/+104
| | | | | | | | | | | | | | | | | Explicitly enable the I2C controller node that is used on each board using the Nuvoton NPCX7 or NPCX9 chipset. This is a no-op at the moment, but prepares for an upstream change that will disable the I2C controller nodes by default. BUG=b:200292035 BRANCH=none TEST=zmake testall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I158ae44090a719ef20930350d89efd7903e6e531 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169389 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Initial port for GuybrushJack Rosenthal2021-09-175-0/+225
| | | | | | | | | | | BUG=b:195137794 BRANCH=none TEST=uart works Change-Id: Ib7e177cfd501f78afb6edf943f078466dca455a6 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168392 Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr: Automatically detect shared I2C portsKeith Short2021-09-141-12/+0
| | | | | | | | | | | | | | | | | | | Delete the "physical-port" node from named-i2c-ports, and automatically detected when multiple children point to the same I2C bus. This ensures that the I2C bus locking always blocks all matching I2C nodes, without the user needing to specify this relationship manually in the devicetree. BUG=none BRANCH=none TEST=Dump out i2c_physical_ports[] on herobrine. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I3d254684483a95af12e7940446f4cd8743684708 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3154694 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Yuval Peress <peress@google.com>
* zephyr: driver: bbram: Migrate to upstream driverYuval Peress2021-09-109-0/+36
| | | | | | | | | | | | | | | | | Migrate the BBRAM driver to the upstream version. BRANCH=none BUG=b:195843756 TEST=zmake testall Cq-Depend: chromium:3147080 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I441e58f94c4874e268aad36df2f036a88187801b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3147230 Tested-by: Yuval Peress <peress@google.com> Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Yuval Peress <peress@google.com>
* zephyr: it8xxx2_evb: enable hibernate mode on it8xxx2_evbTim Lin2021-09-101-2/+8
| | | | | | | | | | | | | | | | | | | | | The GPIO interrupts that can be waked up in hibernate mode include GPIO_LID_OPEN and GPIO_POWER_BUTTON_L. BUG=b:198305804 BRANCH=none TEST=test1: console command: hibernate Wake-up GPIO interrupt: GPIO_LID_OPEN and GPIO_POWER_BUTTON_L test pass! test2: console command: hibernate [seconds] [microseconds] After the specified seconds, the EC will wake-up from sleep mode. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: I4069ec13d2681015a66fddf8d52666371da6048a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3146775 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: asurada: Adjust task stack sizesDenis Brockus2021-09-091-9/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack sizes should be near 75% usage. kernel stacks 21-09-08 16:07:25.972 0x8010af00 PD_C1 (real size 1024): unused 248 usage 776 / 1024 (75 %) 21-09-08 16:07:25.988 0x8010add8 PD_C0 (real size 1024): unused 272 usage 752 / 1024 (73 %) 21-09-08 16:07:26.000 0x8010acb0 KEYSCAN (real size 928): unused 240 usage 688 / 928 (74 %) 21-09-08 16:07:26.013 0x8010ab88 HOSTCMD (real size 1024): unused 272 usage 752 / 1024 (73 %) 21-09-08 16:07:26.026 0x8010aa60 MOTIONSENSE (real size 928): unused 240 usage 688 / 928 (74 %) 21-09-08 16:07:26.038 0x8010a938 CHIPSET (real size 832): unused 224 usage 608 / 832 (73 %) 21-09-08 16:07:26.051 0x8010a810 CHARGER (real size 960): unused 240 usage 720 / 960 (75 %) 21-09-08 16:07:26.062 0x8010a6e8 USB_CHG_P1 (real size 800): unused 192 usage 608 / 800 (76 %) 21-09-08 16:07:26.075 0x8010a5c0 USB_CHG_P0 (real size 800): unused 272 usage 528 / 800 (66 %) 21-09-08 16:07:26.089 0x8010a498 HOOKS (real size 672): unused 352 usage 320 / 672 (47 %) 21-09-08 16:07:26.100 0x80101a08 sysworkq (real size 1024): unused 288 usage 736 / 1024 (71 %) 21-09-08 16:07:26.112 0x801017c8 shell_uart (real size 1056): unused 244 usage 812 / 1056 (76 %) 21-09-08 16:07:26.125 0x80101888 idle 00 (real size 256): unused 128 usage 128 / 256 (50 %) 21-09-08 16:07:26.137 0x80101948 main (real size 1024): unused 344 usage 680 / 1024 (66 %) 21-09-08 16:07:26.150 0x80109cf0 IRQ 00 (real size 800): unused 296 usage 504 / 800 (63 %) BUG=none BRANCH=none TEST=ec console 'kernal stacks' Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I69a0767e4694a386dd24c95b162d92aad5cbebc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3150067 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* herorbrine_npcx9: Use PCF85063A RTC Zephyr driverSam Hurst2021-09-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the RTC driver from the Zephyr MTC driver to the Zephyr PCF85063A driver. BRANCH=none BUG=b:194710429 TEST=ectool rtcset 30000 ectool rtcget Current time: 0x0000753d (30013) ectool rtcsetalarm 10 after ~10 (measured with a timer) printed on ec console: [160.248900 event set 0x0000000002000000] I tested the alarm up to one hour. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6e6f8bb65cb515e0997687ff4beef7620506a57d herorbrine_npcx9: Configure PCF85063A RTC Alert Configure the PCF85063A RTC Alert pin so that it can interrupt the EC on an alarm event. BRANCH=none BUG=b:194710429 TEST=ectool rtcset 30000 ectool rtcget Current time: 0x0000753d (30013) ectool rtcsetalarm 10 after ~10 (measured with a timer) printed on ec console: [160.248900 event set 0x0000000002000000] I tested the alarm up to one hour. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I58ac585c2d566d306625dd8034377925eba36293 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140328 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: it8xxx2: use half space (512KB) from flashDino Li2021-08-171-11/+0
| | | | | | | | | | | | | | | | This saved about 3 seconds erasing time while running software sync. This also pull configurations of flash/memory layout to chip level. BRANCH=none BUG=b:195954913 TEST=software sync successfully. (without erase timeout patch of depthcharge) Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ia7fa08fdf6bdde4c47ca8d852f8eeaa83f39dae5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097250 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: npcx_evb: add the PSL hibernate wake-up pinsJun Lin2021-08-171-0/+16
| | | | | | | | | | | | | | | | | | | | Add PSL_IN1/PSL_IN2/PSL_IN3 as the hibernate wakeup pins. Also map the non-PSL (low power RAM) hibernate wakeup source to the same pads. (i.e. GPIOD2/GPIO00/GPIO01.) Then we can use either PSL hibernate mode (CONFIG_PLATFORM_EC_HIBERNATE_PSL=y) or non-PSL hibernate mode (CONFIG_PLATFORM_EC_HIBERNATE_PSL=n) on the EVB. BUG=none BRANCH=none TEST=pass "zmake testall" TEST='hibernate' & wake-up ec by those wakeup pins. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I4175bdabee138c7bac25f8b43774268ae336d989 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3089083 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* zephyr: npcx_evb: Enable RTCWealian Liao2021-08-161-0/+1
| | | | | | | | | | | | | This CL enables RTC for npcx7/9_evb. BUG=none BRANCH=none TEST='rtc' console command Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Icc5d79d16ba2e4073ce39d38f0942a050d128e82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088961 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: asurada: set CONFIG_HOSTCMD_DEBUG to HCDEBUG_OFFDenis Brockus2021-08-121-0/+4
| | | | | | | | | | | | | | | BUG=b:195948807 BRANCH=none TEST=zmake configure -b $PROJ_HAYATO TEST=boot and verify non-error [HC 0x%x] output does not happen Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Idd872d7d61c04efc71dc843fa7d6b1438dd89ed0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087620 Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: npcx_evb: Enable KeyboardWealian Liao2021-08-121-0/+26
| | | | | | | | | | | | | | | | | | This CL enables keyboard function for npcx7/9_evb. The keyboard sets to the following config: * kso0-12 are selected for keyboard scan * enable CONFIG_CROS_KB_RAW_NPCX_KSO_HIGH_DRIVE * set keyscan_config to meet the config in npcx_evb board.c BRANCH=none BUG=none TEST='ksstate on' & check actual key setting Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I059e1f8d07558a0f465769ecffd4246dcda1a608 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3077764 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: npcx_evb: Enable power managementWealian Liao2021-08-052-0/+12
| | | | | | | | | | | | | This CL enables power management for npcx7/9_evb BUG=none BRANCH=none TEST=Check evb can enter sleep by 'idlestats' console command Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I3ef9776f492388b2943a42d99686de952c7def05 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3068843 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: npcx_evb: Enable PWMWealian Liao2021-07-302-0/+8
| | | | | | | | | | | | | | | | | | | | This CL enables 2 PWM channels for npcx7/9_evb. BRANCH=none BUG=none TEST='pwmduty' console command & check the output waveform is correct. ``` uart:~$ pwmduty PWM channels: 0: 50% 1: 25% ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I6fa5d3b7fd3bf1f9d1fdb3f64ca3488ad3addacc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063104 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: npcx_evb: Enable ADCWealian Liao2021-07-303-0/+42
| | | | | | | | | | | | | | | | | | | | | | This CL enables 5 ADC channels for npcx7/9_evb. BUG=none BRANCH=none TEST='adc' console command ``` uart:~$ adc ADC0 = 2813 mV ADC1 = 2813 mV ADC2 = 2813 mV ADC3 = 2813 mV ADC4 = 2813 mV ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I08d60dc732f7388642a54eec090ef7bf15760a2a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063103 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: npcx_evb: Enable I2CWealian Liao2021-07-293-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL enables I2C for npcx7/9_evb. Currently, zephyr-OS ec doesn't use the GPIO for i2c unwedge functionality. Remove the GPIO setting for i2c in gpio.dts. BUG=none BRANCH=none TEST=Get sensor value by `i2c` shell command ``` uart:~$ i2c scan I2C_2_PORT_0 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: -- -- -- -- -- -- -- -- -- -- -- -- 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40: -- -- -- -- -- -- -- -- 48 -- -- -- -- -- -- -- 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70: -- -- -- -- -- -- -- -- 1 devices found on I2C_2_PORT_0 uart:~$ i2c read I2C_2_PORT_0 0x48 0x00 2 00000000: 1f 80 ``` Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: If5029c41b7ba5400ee1492b408f7ab6975218c5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060348 Reviewed-by: Yuval Peress <peress@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org>
* zephyr: asurada: correct RO/RW size and offsetDino Li2021-07-291-3/+3
| | | | | | | | | | | | | | | | | | it8xxx2's memory-mapped flash layout are as the below: - RO image starts at the beginning of flash. - PSTATE immediately follows the RO image. - RW image starts at the second half of flash. And its flash size is 1M byte. So let's correct RO/RW size and offset. BRANCH=none BUG=b:194794622 TEST=sysjump rw/ro, sysinfo. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1130d670af054d88f7dfd1874ba5ecfd22b500df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058156 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: Initial image for npcx_evb/npcx9Wealian Liao2021-07-274-0/+61
| | | | | | | | | | | | | | | | Initial image for npcx_evb/npcx9 supporting basic UART functionality and basic commands. BUG=none BRANCH=none TEST=test basic console functionality on npcx9_evb Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I0cdf12823df35ec6aaba7a48c5d1698cc814703a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033231 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: Initial image for npcx_evb/npcx7Wealian Liao2021-07-275-0/+91
| | | | | | | | | | | | | | | | Initial image for npcx_evb/npcx7 supporting basic UART functionality and basic commands. BUG=none BRANCH=none TEST=test basic console functionality on npcx7_evb Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Ibdf1ce98b6ad747dc649b82f12e555e63569036a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3033230 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: it8xxx2: shi: enable CS interruptDino Li2021-07-271-0/+5
| | | | | | | | | | | | | | | This interrupt will be needed in the future to enable low power mode on idle task in S0 state. BRANCH=none BUG=b:185176098 TEST=the interrupt can be triggered correctly on asurada. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I04b066de0129f01adf2c7ba4c9f60788b3d46cbc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3034781 Reviewed-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: asurada: enable _EVENT_WAKEUP_MASKDino Li2021-07-271-0/+18
| | | | | | | | | | | | | Only allow the defined MKBP events to wake host up. BRANCH=none BUG=none TEST=Running suspend test x50. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I978a3db3ac0da6e761b8f953e2e89c97b9cbc23e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3053135 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: fix MKBP_HOST_EVENT_WAKEUP_MASKDawid Niedzwiecki2021-07-231-10/+11
| | | | | | | | | | | | | | | | | | MKBP_HOST_EVENT_WAKEUP_MASK is right-shifted by 1 bit, so adjust defining it in the dts. The bug is impacting the waking up DUT with a host event, e.g. EC_HOST_EVENT_RTC which is used during the firmware_EventLog test. BUG=b:193495066 BRANCH=none TEST=Suspend DUT with powerd_dbus_suspend, and make sure the EC command "hostevent set 0x0000000002000000" wakes up the board. Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I253d0dc36cf216fe50a6473c3640fe906ef565e3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3031542 Reviewed-by: Simon Glass <sjg@chromium.org>
* zephyr: i2c: protect physical portDino Li2021-07-221-0/+12
| | | | | | | | | | | | | | | | | | If i2c devices are connected to the same port, they should use the same mutex_lock() index. So the new transaction won't break the ongoing transaction. BRANCH=none BUG=b:189855648 TEST=Enable CONFIG_SMBUS_PEC and voltage regulator function on asurada. No i2c transaction is broken. Change-Id: Ib848e3c2e60b99ce66ad5fd2fc7095f90820a15d Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3010920 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* zephyr: herobrine: Move I2C related dts from board to projectWai-Hong Tam2021-07-201-96/+0
| | | | | | | | | | | | | Make the board dts file simpler and easier to be merged to other boards which use the same chip. BRANCH=None BUG=b:192253134, b:193814903 TEST=Built the Zephyr herobrine_npcx9 image successfully. Change-Id: I53a15a47511eb875bbfd50906f5a11d3a69d48ea Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039387
* zephyr: herobrine_npcx9: Update GPIOsWai-Hong Tam2021-07-201-7/+0
| | | | | | | | | | | | | | | | | This CL is a Zephyr-equivalent of CL:2993217. Update the GPIOs to match the schematic. Also update the hibnerate wake sources. Remove the AP_RST_L and WARM_RESET_L from the low voltage dts as their new GPIOs already operate at 1.8V, not configurable. BRANCH=None BUG=b:192253134, b:193583152 TEST=Built the Zephyr herobrine_npcx9 image successfully. Change-Id: I2fcb03acff7ac376a5627f66c800d2d8cade1998 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039386 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: herobrine_npcx9: Initial image which uses NPCX9Wai-Hong Tam2021-07-204-0/+308
| | | | | | | | | | | | | | | | | | | | | | | This CL copies the Zephyr board/trogdor to board/herobrine_npcx9. Modify the chip config to npcx9m3f and some related configs (simply rename) and dts (update the UART property). The board/herobrine_npcx9 and other NPCX9 boards, like board/brya will be merged to a single board. But the merge needs more work to remove the not-common configs and dts to the project directories. Leave it as a future work. This CL also copies the project trogdor/herobrine_npcx7 to herobrine/herobrine_npcx9. Remove the dead files power.c and hibernate.c, in the EC-OS directory. Remove the Zephyr 2.5 support and board.cmake (needed only for 2.5). BRANCH=None BUG=b:192253134 TEST=Built the herobrine_npcx9 image successfully. Change-Id: I9641768ee978920f6a8677f13ae14e0a26ad35f4 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993220 Reviewed-by: Yuval Peress <peress@chromium.org>
* zephyr: asurada: increase watchdog timer timeoutDenis Brockus2021-07-191-0/+1
| | | | | | | | | | | | | | | BUG=b:193465122 BRANCH=none TEST=verify no "Watchdog deadline is close" on boot Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I84e4c37faa64e4f556bda924ad18e4ccb47039ac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039958 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: move all the boards directories under zephyr/boardsJack Rosenthal2021-07-1629-0/+2025
Move all the boards directories together under zephyr/boards from their scattered locations under projects/. This is the first step towards de-coupling the concept of a Zephyr board from baseboard/board/model, as it currently is. Further work will be required to actually unify these directories and delete the baseboard-specific names from our tree. BUG=b:193814903 BRANCH=none TEST=zmake testall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I33a344af6890b2c2c54f1e91f0f0fa85caaf19d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035222 Commit-Queue: Yuval Peress <peress@chromium.org> Reviewed-by: Yuval Peress <peress@chromium.org>
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