| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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Explicitly enable the I2C controller node that is used on each board
using the Nuvoton NPCX7 or NPCX9 chipset.
This is a no-op at the moment, but prepares for an upstream change that
will disable the I2C controller nodes by default.
BUG=b:200292035
BRANCH=none
TEST=zmake testall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I158ae44090a719ef20930350d89efd7903e6e531
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169389
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The PS8805 supports 1 MHz operation normally, but only 400 kHz operation
during flash updates. The I2C passthru interface used by depthcharge
doesn't support changing the I2C frequency or informing the EC that a
firmware update is going to start, so the lower frequency must be used.
BUG=b:199550987
BRANCH=none
TEST=Verify PS8805-A3 firmware updates
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I9be242ce03cc29c74559c6012b5cc83680b7b288
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3166998
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Change the RTC driver from the Zephyr MTC driver to
the Zephyr PCF85063A driver.
BRANCH=none
BUG=b:194710429
TEST=ectool rtcset 30000
ectool rtcget
Current time: 0x0000753d (30013)
ectool rtcsetalarm 10
after ~10 (measured with a timer) printed on
ec console: [160.248900 event set 0x0000000002000000]
I tested the alarm up to one hour.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6e6f8bb65cb515e0997687ff4beef7620506a57d
herorbrine_npcx9: Configure PCF85063A RTC Alert
Configure the PCF85063A RTC Alert pin so that
it can interrupt the EC on an alarm event.
BRANCH=none
BUG=b:194710429
TEST=ectool rtcset 30000
ectool rtcget
Current time: 0x0000753d (30013)
ectool rtcsetalarm 10
after ~10 (measured with a timer) printed on
ec console: [160.248900 event set 0x0000000002000000]
I tested the alarm up to one hour.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I58ac585c2d566d306625dd8034377925eba36293
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140328
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL is a Zephyr-equivalent of CL:2993218.
Add the I2C bus for the RTC chip. The chip runs at 400KHz.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: I399485706c66070464fcd9fe53bec35b4c0454a6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039388
Reviewed-by: Yuval Peress <peress@chromium.org>
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Make the board dts file simpler and easier to be merged to other boards
which use the same chip.
BRANCH=None
BUG=b:192253134, b:193814903
TEST=Built the Zephyr herobrine_npcx9 image successfully.
Change-Id: I53a15a47511eb875bbfd50906f5a11d3a69d48ea
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039387
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