| Commit message (Collapse) | Author | Age | Files | Lines |
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NPCX BBRAM module provides VBAT/VSBY/VCC power drop information. The
status bit will set when the chip power-up or hibernate PSL wake-up,
which provides the false error alarm. This CL changes the power drop
information to LOG_INF.
BUG=none
BRANCH=none
TEST=Check the log with LOG_LEVEL_INF.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I36bafedbc694333236ae8824310cfdfcceab7ac8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180704
Reviewed-by: Aaron Massey <aaronmassey@google.com>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Note that currently CONFIG_SYSCON=y is required. There's an ongoing
PR (https://github.com/zephyrproject-rtos/zephyr/pull/38762) to remove
that requirement in favor of simply detecting an enabled node in DT
via the compatible string.
BRANCH=none
BUG=b:179900857, b:165777478, b:200642229
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@google.com>
Change-Id: Idad1f53afbda503e0e0b2fdf2931d5267a391d4d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3177749
Reviewed-by: Sam Hurst <shurst@google.com>
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This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244.
Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO.
Original change's description:
> npcx: correct the image copies indication bits for npcx9
>
> In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
> of the MDC register) to indicate what the current image copy is.
> In npcx9, these two bits are used by the booter. We need to change them
> to another two empty scratch bits which are not used by the booter.
>
> BUG=b:165777478
> BRANCH=none
> TEST=pass "make buildall"
> TEST=check the related bits changed by "sysump ro" and "sysjump rw"
>
> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: caveh jalali <caveh@chromium.org>
> Auto-Submit: CH Lin <chlin56@nuvoton.com>
> Commit-Queue: caveh jalali <caveh@chromium.org>
Bug: b:165777478
Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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Migrate the BBRAM driver to the upstream version.
BRANCH=none
BUG=b:195843756
TEST=zmake testall
Cq-Depend: chromium:3147080
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I441e58f94c4874e268aad36df2f036a88187801b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3147230
Tested-by: Yuval Peress <peress@google.com>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Yuval Peress <peress@google.com>
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Compile the NPCX monitor code under the Zephyr environment.
BUG=b:197162681
BRANCH=none
TEST=Build zephyr for volteer. Verify npcx_monitor.bin is created.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Idba6e013288eb9c300c91ea57313db08e13b2e97
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3116567
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: CH Lin <chlin56@nuvoton.com>
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This code was added after v2.5 was already dropped from the tree.
These macros are not necessary.
BUG=b:197159539
BRANCH=none
TEST=zmake testall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Idbbf3d6431542a707f5abe954b56838a4b18403b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104787
Commit-Queue: Yuval Peress <peress@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
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This saved about 3 seconds erasing time while running software sync.
This also pull configurations of flash/memory layout to chip level.
BRANCH=none
BUG=b:195954913
TEST=software sync successfully.
(without erase timeout patch of depthcharge)
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ia7fa08fdf6bdde4c47ca8d852f8eeaa83f39dae5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097250
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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We no longer support version 2.5. Drop these obsolete ifdefs.
BUG=b:195571108
BRANCH=none
TEST=zmake testall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I85985108bcf175a2756a2f8096b0aa9e3c22fce5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086368
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
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Follow PR:37194 to access KBC/ACPI event data via structure if the
Zephyr version is v2.6. Otherwise, use the original chip-vendor-specific
macro on version v2.5.
BUG=none
BRANCH=none
TEST=pass "zmake testall"
TEST=test on Volteer, verify that the platform can boot up to OS screen;
make sure keyboard is functional.
Cq-Depend: chromium:3054142
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Iff857809b3c11e734825c113cb8d9913a7a177f2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3053140
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Zephyr NPCX drivers has been switched to the link time device
definition, and now NPCX_CLK_CTRL_NODE is available to point to the pcc
node directly. Use that in the EC code as well for the clock API.
BRANCH=none
BUG=none
TEST=build and run on volteer
Cq-Depend: chromium:3000806, chromium:3070703
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I8a5b5426c5e6a9167cd232fc72e50d372958b31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3001584
Reviewed-by: Yuval Peress <peress@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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NPCX & IT8xxx2 series are both use BBRAM for scratchpad/reset_flags
access. cros_bbram API already handles the chip-specific code. This CL
moves scratchpad/reset_flags access functions to the common system.c to
avoid duplicate those functions.
BUG=none
BRANCH=none
TEST=zmake testall
TEST=check reset cause on lazor & npcx_evb
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I0a394e5fbf784ec2e3caea77f194c88ae9d5542e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067156
Reviewed-by: Yuval Peress <peress@chromium.org>
Commit-Queue: Yuval Peress <peress@chromium.org>
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ITE, can you verify using base for the reset vector
lines up with where you expect the reset vector to be
in the image
BUG=b:194794622
BRANCH=none
TEST=zmake configure -b $PROJ_HAYATO
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: Id66c1613e4a89aad36f68a8d03d3079f9d035e94
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3056513
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Allow building the zephyr/shim/src/espi.c for other SOCs by adding
inline functions to abstract away these concepts. Each SOC should
then implement these under the zephyr/shim/chip/<soc> specific
directory.
BRANCH=none
BUG=b:189954415
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I776bd65326b509ada3b271177ae727a32d4f96da
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044400
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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UPSTREAM PR(https://github.com/zephyrproject-rtos/zephyr/pull/36663)
adds the chip ID information.
```
soc-id {
compatible = "nuvoton,npcx-soc-id";
family-id = <0x20>;
chip-id = <0xXX>;
device-id = <0xXX>;
revision-reg = <0xXXXXXXXX X>;
};
```
This CL changes chip information API to use the UPSTREAM devicetree
node.
For the get_chip_name(), change to compare the ID at devicetree node &
return the build part number or the chip id.
BUG=none
BRANCH=none
TEST=zmake testall
TEST='version' console command
Cq-Depend: chromium:3010788, chromium:3010789
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ic10c9671ecf466649dbb90a3b4acda97df4f823a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000362
Reviewed-by: Keith Short <keithshort@chromium.org>
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The function call has been removed in v2.6, changing the version
condition to exclude it entirely so it's clear that it can be dropped
once we drop support for v2.5.
BRANCH=none
BUG=b:186651036
TEST=build tested
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: Icbf4d06e6d7e8f4910dde66b89dceadc4b6f39ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000246
Reviewed-by: Yuval Peress <peress@chromium.org>
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UPSTREAM has NPCX_PWDWN_CTL definition. This CL transfers to use
UPSTREAM NPCX_PWDWN_CTL macro to fix the redefine warning.
BRANCH=none
BUG=none
TEST=build byra without warning
TEST='sysjump RW' is correct
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ib92f2263f3e10cae5d8b0ebd4f3b274c8c7359a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994229
Reviewed-by: Yuval Peress <peress@chromium.org>
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Convert various device_get_binding to DEVICE_DT_GET, which is processed
at link time and more efficient. Same pattern on different modules where
the output is checked using device_is_ready.
BRANCH=none
BUG=none
TEST=zmake configure -b -B ~/build-volteer/ zephyr/projects/volteer/volteer
TEST=zmake configure -b -B ~/build-it8xxx2_evb/ zephyr/projects/it8xxx2_evb
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: If426420da2c61b3bc02eb77e122469a1a40799f7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985463
Reviewed-by: Yuval Peress <peress@chromium.org>
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This changes the clock control calls to use DEVICE_DT_GET instead of
device_get_binding. DEVICE_DT_GET is more efficient since it's allocated
at link time.
These are then used by clock_control_on, which already checks for
device_is_ready, so no extra safety checks are needed.
BRANCH=none
BUG=none
TEST=zmake configure -b -B ~/build-volteer/ zephyr/projects/volteer/volteer
TEST=zmake configure -b -B ~/build-it8xxx2_evb/ zephyr/projects/it8xxx2_evb
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change-Id: I76a2c47165d197c799be25d8e7e40a1a0873777d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985462
Reviewed-by: Yuval Peress <peress@chromium.org>
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These flash related configs have to be enabled for the flash driver
of it8xxx2.
This CL also distinguishes the flash configs into header file of
it8xxx2 and npcx.
BUG=b:187192628
BRANCH=none
TEST=zmake -lDEBUG configure -b -B zephyr/build_ite \
zephyr/projects/it8xxx2_evb
zmake -lDEBUG configure -b -B zephyr/build_volteer \
zephyr/projects/volteer/volteer
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: Ic6a2e89a24676d6ac484a389c938ab0692971be0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2952280
Reviewed-by: Keith Short <keithshort@chromium.org>
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The configurations of pinmux have been moved to
the header file of it8xxx2-pinctrl.h.
BUG=b:185202623
BRANCH=none
TEST=pinmux control is normally.
Cq-Depend: chromium:2964460
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I2ee179f660fdc4a15c3d6a8630988d77134bb4b1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905677
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Update power_policy.c to support API changes in v2.6.
BRANCH=none
BUG=b:190731415
TEST=build brya with both 2.5 and 2.6
Change-Id: I757b465e03f8da30e1f00d6bde8234e1434e90db
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2970988
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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BRANCH=none
BUG=b:188605676
TEST=run `sysjump RW` on brya
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: Ic771a0452cd044355dd2a0e0f32fa6e2d3711a44
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936009
Reviewed-by: Keith Short <keithshort@chromium.org>
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This function is needed for the flash api workaround.
BRANCH=none
BUG=b:188605676
TEST=build brya
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I3ddd72e7664755f07bc967695b1502a43af3e57a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936008
Reviewed-by: Keith Short <keithshort@chromium.org>
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This function is taken from chip/npcx/ and is used for the flash
workaround.
BRANCH=none
BUG=b:188605676
TEST=build brya
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I70775523d180a602c08f7059f0fe003c05007edf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936007
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BRANCH=none
BUG=b:188605676
TEST=build brya
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I900f4af147e048a374b56875579d838deaa17eae
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2936006
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Add clock to support it8xxx2 cros_kb_row driver.
BUG=b:187192587
BRANCH=none
TEST=on hayato, read pll_reg_to_freq is same as setting.
Cq-Depend: chromium:2909732
Change-Id: I9fd9f6ca5c6796ad9aee22a5cf7dc23564d2a814
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2813880
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Add support for it8xxx2 cros_kb_row driver.
BUG=b:187192587
BRANCH=none
TEST=on hayato, console cmd "ksstate" then press key:
[115.097839 KB state: -- -- -- 02 -- -- 02 -- -- -- -- -- --]
[116.462371 KB state: -- -- -- -- -- -- 02 -- -- -- -- -- --]
[116.499633 KB state: -- -- -- -- -- -- -- -- -- -- -- -- --]
Cq-Depend: chromium:2902165
Change-Id: I067b95bf2dfe4978e5370ce27382c67db100467b
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784322
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Move shim/chip/npcx/keyboard_raw.c most functions to
shim/src/keyboard_raw.c.
BUG=none
BRANCH=none
TEST=zmake -lDEBUG configure -B zephyr/build
-b zephyr/projects/volteer/volteer
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: Ic69752223517cabb9e1d1c7ff16c9eb4914186db
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2900122
Reviewed-by: Keith Short <keithshort@chromium.org>
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Enable i2c ports alt function with new pinmux driver.
BUG=b:187043683
BRANCH=none
TEST=On Asurada, verify I2C ports' alt function are set correctly.
Cq-Depend: chromium:2857993
Signed-off-by: Denis Brockus <dbrockus@google.com>
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I816aa7e9f9aff1eecf3ebcd55bf822f0e66cdff3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2858298
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
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Add power management support for the NPCX family.
BUG=b:184653704
BRANCH=none
TEST=zmake testall
TEST=Verify deep sleep on Volteer (with next CL) and measure power.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I86eef50c13742e7ca717da38a92636e589af6c58
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855527
Reviewed-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
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This is a temporary piece of code that will be adjusted
and/or removed when driver/pinmux/pinmux_ite_it8xxx2.c
is released. The temporary code allows UART to work,
so it is being added for now.
BUG=b:185202623
BRANCH=none
TEST=none
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: I3f100f6a4cefea86f1e00a0a542ccd7f38f44878
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848434
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
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BUG=b:185202623
BRANCH=none
TEST=none
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: Ia6e3821bb23b5aa928aa62ebc06abc0b1e9f8618
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848433
Tested-by: Denis Brockus <dbrockus@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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This CL adds ununed GPIOs configuration support in shimmed gpio driver.
By adding IO phandles in 'unused-gpios' prop of board device-tree file,
the shimmed driver will configure them one by one (depends on board
circuit or io-pad design in chip) to prevent leakage current and get
better power consumption in the lowest power state.
BUG=b:184783076
BRANCH=none
TEST=zmake testall
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ia4fe29cc244e27855faa1b57c2d1f8319b1246c3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2817141
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Add NPCX chip_vendor(), chip_name(), and chip_revision implementation
for cros_system driver.
BUG=none
BRANCH=none
TEST=Build & boot ec on volteer.
TEST=Press 'version' in console and show related chip information:
```
21-04-06 17:53:00.681 uart:~$ version
21-04-06 17:53:01.795 Chip: Nuvoton NPCX796FC 02
21-04-06 17:53:01.795 Board: 2
21-04-06 17:53:01.795 RO: _v2.0.8287+db38ffd6d
21-04-06 17:53:01.795 RW: _v2.0.8287+db38ffd6d
21-04-06 17:53:01.795 Build: _v2.0.8287+db38ffd6d
```
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I73d016f5fa1da6c03e38b312eb4f1b0445a2c1d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2807479
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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This is the follow-up CL to fix the bug addressed in the comment of the
CL:2786888
BUG=b:182600858
BRANCH=none
TEST=pass zmake build
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Id1923f3dc0ac357cbcac876a5e68f304024867ba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2799336
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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BUG=b:182600858
BRANCH=none
TEST=Test host command "version" and "Hello" on npcx7_evb and the host
emulator.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ie9424d9e68a04f575bc6f695b29ca64f14147eef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2786888
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
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Remove the CHIP_FAMILY_ and CHIP_VARIANT_ preprocessor definitions that
are not used.
BUG=none
BRANCH=none
TEST=zmake testall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ied1d49495109ea99029196d4ad65462381c2581b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2777124
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The upstream Zephyr repo does not support LTO. Reconfigure the
platform/ec source files into a cmake library so the LTO option can be
enabled for all the platorm/ec sources.
This reduces the Volteer flash image size by 9176 bytes.
BUG=none
BRANCH=none
TEST=zmake testall
TEST=boot zephyr-ec on Volteer, verfiy AP boots
Cq-Depend: chromium:2776218
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I8312773c8b21c498ec8116a8558b7571831159ff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2776217
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The reset cause will influence the initialization flow. We define some
of initial flow of the reset cause for the following development.
This CL include the following:
1. Add check_reset_cause() which sets the system reset flag.
2. Add chip_bbram_status_check() to clear the error status & show the
error message.
3. Add CONFIG_BOARD_RESET_AFTER_POWER_ON feature.
4. Define the initialize flow for reset cause.
BRANCH=none
BUG=b:178101173
TEST=check the following reset cause by 'sysinfo'
1. power-up
2. reset-pin reset
3. soft by 'reboot' console command
4. watchdog by 'waitms 2000'
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I515868d8cda4544fdbe782210b0108b4dda0d8cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731180
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Implement the following functions in Zephyr:
1. clock_turbo
2. clock_normal
3. clock_enable_module
With these, the CPU clock can speeds up when computing the hash value
and goes back to normal when the computation is done.
BRANCH=none
BUG=b:182224114
TEST=Volteer no longer watchdog resets and can boot up to ChromeOS
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I419cf68c4212fdc588b9fd2a08331c4e81ccf0a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748197
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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CHIP_FAMILY only gets set for the npcx7m6fb chip, but all nuvoton
chips appear to need this directory.
BUG=b:182410932,b:182398910
BRANCH=none
TEST=compile for lazor using npcx7m6fc chip configuration
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I9e6a152b8c31c1bcd3141591863a7b78e03e3766
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2749422
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL adds chip_save_reset_flags() & chip_read_reset_flags(). Also,
fulfill the system_reset()
BUG=b:176523207
BRANCH=None.
TEST=check 'reboot wait-ext' will wait 10s
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Idb9c2e90e8ad5e8a989f33ac904c3b778b8f48e4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2731179
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL include the following:
1. Add cros_system_soc_reset() API for system reset.
2. Add NPCX soc reset driver. NPCX chip doesn't have the specific
system reset functionality. Use watchdog reset as the system reset.
BUG=b:176523207
BRANCH=None.
TEST=reset EC by 'reboot' console command
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ia86bfac548ef48e18e501a29f3cbb632f33a3e8a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698739
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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This gives a warning about a duplicate definition since it is defined
in Zephyr now.
BUG=b:180409973
BRANCH=none
TEST=warning is gone
Change-Id: I6d7a7b5f344bf6ab4168a2dee062c9199175faf9
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2705443
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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In order to sysjump we first need to copy the RW image from flash.
rom_chip.h adds a macro to call ROM function download_from_flash
(while system_external_storage.c contains all the npcx specific code
needed to perform the sysjump).
BRANCH=none
BUG=b:167392037
TEST=zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I762954a71e87036b63513ae8b400605ed507fcf6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2693527
Reviewed-by: Simon Glass <sjg@chromium.org>
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Some functionality (sysjump in particular) makes use of altering the
clock rate. This should eventually live in Zephyr proper, but for
now stubbing it will get things working, just a bit slower.
BRANCH=none
BUG=b:167392037, b:180112248
TEST=zmake testall
TEST=build volteer, flash, see that it runs.
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I91ff57c7e0f5cda60556087e6c46ba1d08f8b4a6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2693526
Reviewed-by: Simon Glass <sjg@chromium.org>
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Kohaku uses the same EC chip as volteer. Adding a second device will
help give us a tiny bit more build diversity too, which is a good
thing probably.
This just adds a minimal build for kohaku with just UART support. No
power sequencing, keyboard, USB-C, charging, etc.
BUG=b:177609422
BRANCH=none
TEST=flash onto kohaku, observe working shell and timers
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I277510081c9e06b516b6c29f790e16dd1dfe8028
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2631361
Reviewed-by: Simon Glass <sjg@chromium.org>
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The CL include the following:
1. Add host command handler. For the Zephyr shim, the host command
handler is invoked by ESPI_PERIPHERAL_EC_HOST_CMD event in
ESPI_BUS_PERIPHERAL_NOTIFICATION eSPI event.
2. Add system_reset() empty function for host command build pass in
shim/ship/npcx/system.c
BRANCH=none
BUG=b:175217186
TEST=Get the host command & show on the console for volteer.
e.g.
[HC 0x0d]
[HC 0x0d err 1]
Cq-Depend: chromium:2603204
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ifd70b9a73c3a2404530182cfc4ce5f3ce4038b49
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2594756
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
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Fix the warning about npcx_get_gpio_dev() not being declared.
BUG=b:174871569
BRANCH=none
TEST=build for zephyr, see the warning gone
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ic0ef6e85baf884fa2c0d0a09044fd1da606e4bb8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2595221
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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