From 030d876ce992a118db08ac66ea48fa65ccf934b5 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Wed, 6 Jul 2022 11:42:46 -0600 Subject: chip/max32660/pwrseq_regs.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Tricium: disable Change-Id: I9b49beabcc3114cee29d67177e94a45466b77922 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3749433 Reviewed-by: Jeremy Bettis --- chip/max32660/pwrseq_regs.h | 59 ++++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h index e84c814ef4..77971adabc 100644 --- a/chip/max32660/pwrseq_regs.h +++ b/chip/max32660/pwrseq_regs.h @@ -171,25 +171,28 @@ typedef struct { Mask */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_0_9V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_0_9V \ + Setting \ + */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_1_0V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_0V \ + Setting \ + */ #define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ - LP_CTRL_OVR_1_1V \ - Setting \ - */ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_1V \ + Setting \ + */ #define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ @@ -378,12 +381,13 @@ typedef struct { * Low Power Mode Wakeup Flags for GPIO0 */ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ -#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ - ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ - LP_WAKEFL_WAKEST \ - \ \ - \ \ \ Mask \ - */ +#define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ + LP_WAKEFL_WAKEST \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers @@ -391,12 +395,13 @@ typedef struct { * power wakeup functionality for GPIO0. */ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ -#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ - ((uint32_t)(0x3FFFUL << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ - LPWK_EN_WAKEEN \ - \ \ - \ \ \ Mask \ - */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ + LPWK_EN_WAKEEN \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers -- cgit v1.2.1