From 05bd0cdec7a3132fda3127c3c9daeed0ebae0dae Mon Sep 17 00:00:00 2001 From: Randall Spangler Date: Fri, 6 Dec 2013 15:17:33 -0800 Subject: Rename mixed-case config constants This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang Reviewed-by: Bill Richardson --- chip/lm4/clock.c | 4 ++-- chip/stm32/clock-stm32f.c | 4 ++-- chip/stm32/config_chip.h | 8 ++++---- chip/stm32/hwtimer.c | 4 ++-- chip/stm32/power_led.c | 2 +- chip/stm32/pwm.c | 4 ++-- chip/stm32/registers.h | 30 +++++++++++++++--------------- chip/stm32/system.c | 6 +++--- chip/stm32/uart.c | 4 ++-- common/flash.c | 4 ++-- common/i2c.c | 2 +- common/pmu_tps65090.c | 2 +- common/usb_port_power_smart.c | 4 ++-- power/gaia.c | 10 +++++----- power/tegra.c | 2 +- test/stress.c | 12 ++++++------ test/test_config.h | 20 ++++++++++---------- 17 files changed, 61 insertions(+), 61 deletions(-) diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c index bb3ca3be30..4fa72c5ca1 100644 --- a/chip/lm4/clock.c +++ b/chip/lm4/clock.c @@ -143,7 +143,7 @@ int clock_get_freq(void) void clock_init(void) { -#ifdef BOARD_bds +#ifdef BOARD_BDS /* * Perform an auto calibration of the internal oscillator using the * 32.768KHz hibernate clock, unless we've already done so. This is @@ -435,7 +435,7 @@ static int command_sleep(int argc, char **argv) if (argc >= 5) flash_pm = strtoi(argv[4], NULL, 10); -#ifdef BOARD_bds +#ifdef BOARD_BDS /* Remove LED current sink. */ gpio_set_level(GPIO_DEBUG_LED, 0); #endif diff --git a/chip/stm32/clock-stm32f.c b/chip/stm32/clock-stm32f.c index 96218f115f..a9fd61fcf0 100644 --- a/chip/stm32/clock-stm32f.c +++ b/chip/stm32/clock-stm32f.c @@ -113,14 +113,14 @@ static void __rtc_alarm_irq(void) } DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1); -#if defined(BOARD_snow) || defined(BOARD_spring) +#if defined(BOARD_SNOW) || defined(BOARD_SPRING) /* * stays on HSI (8MHz), no prescaler, PLLSRC = HSI/2, PLLMUL = x4 * no MCO => PLLCLK = 16 Mhz */ #define DESIRED_CPU_CLOCK 16000000 #define RCC_CFGR 0x00080000 -#elif defined(BOARD_mccroskey) +#elif defined(BOARD_MCCROSKEY) /* * HSI = 8MHz, no prescaler, no MCO * PLLSRC = HSI/2, PLLMUL = x12 => PLLCLK = 48MHz diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 4ae81b2e51..2d439a800e 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -13,14 +13,14 @@ #define CONFIG_UART_CONSOLE 1 /* Use variant specific configuration for flash / UART / IRQ */ -#if defined(CHIP_VARIANT_stm32l15x) +#if defined(CHIP_VARIANT_STM32L15X) #include "config-stm32l15x.h" -#elif defined(CHIP_VARIANT_stm32l100) +#elif defined(CHIP_VARIANT_STM32L100) #include "config-stm32l100.h" -#elif defined(CHIP_VARIANT_stm32f100) +#elif defined(CHIP_VARIANT_STM32F100) /* STM32F100xx is currently the only outlier in the STM32F series */ #include "config-stm32f100.h" -#elif defined(CHIP_VARIANT_stm32f10x) +#elif defined(CHIP_VARIANT_STM32F10X) /* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx, and STM32F107xx */ #include "config-stm32f10x.h" #else diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c index abd2d2ba7b..0d238b53d4 100644 --- a/chip/stm32/hwtimer.c +++ b/chip/stm32/hwtimer.c @@ -169,12 +169,12 @@ void __hw_timer_enable_clock(int n, int enable) * Mapping of timers to reg/mask is split into a few different ranges, * some specific to individual chips. */ -#if defined(CHIP_FAMILY_stm32f) +#if defined(CHIP_FAMILY_STM32F) if (n == 1) { reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM1; } -#elif defined(CHIP_FAMILY_stm32l) +#elif defined(CHIP_FAMILY_STM32L) if (n >= 9 && n <= 11) { reg = &STM32_RCC_APB2ENR; mask = STM32_RCC_PB2_TIM9 << (n - 9); diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c index 976ab0208f..3c391dab86 100644 --- a/chip/stm32/power_led.c +++ b/chip/stm32/power_led.c @@ -64,7 +64,7 @@ static void power_led_manual_off(void) * configure it as an open-drain output and set it to high impedence, * but reconfiguring as an input had better results in testing. */ -#ifdef BOARD_snow +#ifdef BOARD_SNOW gpio_set_flags(GPIO_LED_POWER_L, GPIO_INPUT); gpio_set_level(GPIO_LED_POWER_L, 1); #else diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index b8683ed9f4..b09b9e7da1 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -38,7 +38,7 @@ static void pwm_configure(enum pwm_channel ch) const struct gpio_info *gpio = gpio_list + pwm->pin; timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); volatile unsigned *ccmr = NULL; -#ifdef CHIP_FAMILY_stm32f +#ifdef CHIP_FAMILY_STM32F int mask = gpio->mask; volatile uint32_t *gpio_cr = NULL; uint32_t val; @@ -47,7 +47,7 @@ static void pwm_configure(enum pwm_channel ch) if (using_pwm[ch]) return; -#ifdef CHIP_FAMILY_stm32f +#ifdef CHIP_FAMILY_STM32F if (mask < 0x100) { gpio_cr = &STM32_GPIO_CRL(gpio->port); } else { diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index ead13c58d1..e1c3cc1a1a 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -133,11 +133,11 @@ #define STM32_TIM6_BASE 0x40001000 #define STM32_TIM7_BASE 0x40001400 #define STM32_TIM8_BASE 0x40013400 /* STM32F10x only */ -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_TIM9_BASE 0x40010800 /* STM32L15X only */ #define STM32_TIM10_BASE 0x40010C00 /* STM32L15X only */ #define STM32_TIM11_BASE 0x40011000 /* STM32L15X only */ -#elif defined(CHIP_VARIANT_stm32f10x) +#elif defined(CHIP_VARIANT_STM32F10X) #define STM32_TIM9_BASE 0x40014C00 /* STM32F10x only */ #define STM32_TIM10_BASE 0x40015000 /* STM32F10x only */ #define STM32_TIM11_BASE 0x40015400 /* STM32F10x only */ @@ -216,7 +216,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define DUMMY_GPIO_BANK GPIO_A -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_GPIOA_BASE 0x40020000 #define STM32_GPIOB_BASE 0x40020400 #define STM32_GPIOC_BASE 0x40020800 @@ -248,7 +248,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define GPIO_ALT_RI 0xE #define GPIO_ALT_EVENTOUT 0xF -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) #define STM32_GPIOA_BASE 0x40010800 #define STM32_GPIOB_BASE 0x40010c00 #define STM32_GPIOC_BASE 0x40011000 @@ -322,7 +322,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_PWR_CR_LPSDSR (1 << 0) #define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04) -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_RCC_BASE 0x40023800 #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) @@ -360,7 +360,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04) #define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) #define STM32_RCC_BASE 0x40021000 #define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00) @@ -425,7 +425,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RTC_BASE 0x40002800 -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00) #define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04) #define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08) @@ -444,7 +444,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_BKP_DATA(n) STM32_RTC_BACKUP(n) #define STM32_BKP_ENTRIES 20 -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) #define STM32_RTC_CRH REG32(STM32_RTC_BASE + 0x00) #define STM32_RTC_CRL REG32(STM32_RTC_BASE + 0x04) #define STM32_RTC_PRLH REG32(STM32_RTC_BASE + 0x08) @@ -459,7 +459,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; /* --- Backup Registers --- */ #define STM32_BKP_BASE 0x40006c00 -#if defined(CHIP_VARIANT_stm32f10x) +#if defined(CHIP_VARIANT_STM32F10X) #define STM32_BKP_ENTRIES 42 #define STM32_BKP_DATA(n) \ REG16(STM32_BKP_BASE + (n < 11 ? 0x4 : 0x40) + 4 * (n)) @@ -521,7 +521,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; /* --- Flash --- */ -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_FLASH_REGS_BASE 0x40023c00 #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) @@ -560,7 +560,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_OPTB_WRP3L 0x18 #define STM32_OPTB_WRP3H 0x1c -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) #define STM32_FLASH_REGS_BASE 0x40022000 #define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00) @@ -602,7 +602,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC2_BASE 0x40012800 /* STM32F10x only */ #define STM32_ADC3_BASE 0x40013C00 /* STM32F10x only */ -#if defined(CHIP_VARIANT_stm32f100) +#if defined(CHIP_VARIANT_STM32F100) #define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) #define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) #define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) @@ -618,7 +618,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_ADC_JSQR REG32(STM32_ADC1_BASE + 0x38) #define STM32_ADC_JDR(n) REG32(STM32_ADC1_BASE + 0x3C + ((n)&3) * 4) #define STM32_ADC_DR REG32(STM32_ADC1_BASE + 0x4C) -#elif defined(CHIP_FAMILY_stm32l) +#elif defined(CHIP_FAMILY_STM32L) #define STM32_ADC_SR REG32(STM32_ADC1_BASE + 0x00) #define STM32_ADC_CR1 REG32(STM32_ADC1_BASE + 0x04) #define STM32_ADC_CR2 REG32(STM32_ADC1_BASE + 0x08) @@ -651,9 +651,9 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; /* --- DMA --- */ -#if defined(CHIP_FAMILY_stm32l) +#if defined(CHIP_FAMILY_STM32L) #define STM32_DMA1_BASE 0x40026000 -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) #define STM32_DMA1_BASE 0x40020000 #else #error Unsupported chip variant diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 41d47218fa..2cd4063709 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -151,14 +151,14 @@ void system_pre_init(void) while (!(STM32_RCC_CSR & (1 << 1))) ; /* re-configure RTC if needed */ -#ifdef CHIP_FAMILY_stm32l +#ifdef CHIP_FAMILY_STM32L if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) { /* the RTC settings are bad, we need to reset it */ STM32_RCC_CSR |= 0x00800000; /* Enable RTC and use LSI as clock source */ STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000; } -#elif defined(CHIP_FAMILY_stm32f) +#elif defined(CHIP_FAMILY_STM32F) if ((STM32_RCC_BDCR & 0x00018300) != 0x00008200) { /* the RTC settings are bad, we need to reset it */ STM32_RCC_BDCR |= 0x00010000; @@ -197,7 +197,7 @@ void system_reset(int flags) if (flags & SYSTEM_RESET_HARD) { -#ifdef CHIP_FAMILY_stm32l +#ifdef CHIP_FAMILY_STM32L /* * Ask the flash module to reboot, so that we reload the * option bytes. diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index f2650591ed..5e21a128d4 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -192,7 +192,7 @@ static void uart_freq_change(void) { int div = DIV_ROUND_NEAREST(clock_get_freq(), CONFIG_UART_BAUD_RATE); -#ifdef CHIP_FAMILY_stm32l +#ifdef CHIP_FAMILY_STM32L if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -254,7 +254,7 @@ void uart_init(void) STM32_USART_CR1(UARTN) |= STM32_USART_CR1_RXNEIE; #endif -#ifdef CHIP_FAMILY_stm32l +#ifdef CHIP_FAMILY_STM32L /* Use single-bit sampling */ STM32_USART_CR3(UARTN) |= STM32_USART_CR3_ONEBIT; #endif diff --git a/common/flash.c b/common/flash.c index 2c613493bf..d39729980b 100644 --- a/common/flash.c +++ b/common/flash.c @@ -626,12 +626,12 @@ static int flash_command_protect(struct host_cmd_handler_args *args) if (!(r->flags & EC_FLASH_PROTECT_RO_NOW)) r->writable_flags |= EC_FLASH_PROTECT_RO_AT_BOOT; -#ifdef CHIP_FAMILY_stm32f +#ifdef CHIP_FAMILY_STM32F /* * TODO(crosbug.com/p/23762): Should ignore all-now on STM32F if WP * isn't asserted. We don't do this due to limitations in early snow * boards (lack of WP GPIO?) - in which case, this can either be - * restricted to BOARD_snow, or removed entirely. + * restricted to BOARD_SNOW, or removed entirely. */ r->valid_flags |= EC_FLASH_PROTECT_ALL_NOW; r->writable_flags |= EC_FLASH_PROTECT_ALL_NOW; diff --git a/common/i2c.c b/common/i2c.c index 2db40bdf21..5e38ddd200 100644 --- a/common/i2c.c +++ b/common/i2c.c @@ -343,7 +343,7 @@ static void scan_bus(int port, const char *desc) watchdog_reload(); /* Otherwise a full scan trips watchdog */ ccputs("."); -#ifdef CHIP_FAMILY_stm32f +#ifdef CHIP_FAMILY_STM32F /* * TODO(crosbug.com/p/23569): The i2c_xfer() implementation on * STM32F can't read a byte without writing one first. So diff --git a/common/pmu_tps65090.c b/common/pmu_tps65090.c index 70b5dbeb2c..cf075c62d0 100644 --- a/common/pmu_tps65090.c +++ b/common/pmu_tps65090.c @@ -621,7 +621,7 @@ static void pmu_chipset_startup(void) { pmu_init(); -#ifdef BOARD_pit +#ifdef BOARD_PIT /* Enable FET4 by default which allows for SD Card booting */ { int pgood; diff --git a/common/usb_port_power_smart.c b/common/usb_port_power_smart.c index 6a60e8a04f..be4cf138a2 100644 --- a/common/usb_port_power_smart.c +++ b/common/usb_port_power_smart.c @@ -32,7 +32,7 @@ static uint8_t charge_mode[USB_CHARGE_PORT_COUNT]; static void usb_charge_set_control_mode(int port_id, int mode) { -#ifdef BOARD_rambi +#ifdef BOARD_RAMBI /* * Rambi has only a single shared control signal, so the last mode set * to either port wins. Also, only CTL1 can be set; the other pins @@ -62,7 +62,7 @@ static void usb_charge_set_enabled(int port_id, int en) static void usb_charge_set_ilim(int port_id, int sel) { -#ifdef BOARD_rambi +#ifdef BOARD_RAMBI /* Rambi has a shared ILIM_SEL signal too */ gpio_set_level(GPIO_USB_ILIM_SEL, sel); #else diff --git a/power/gaia.c b/power/gaia.c index e51eab25e0..b928a00719 100644 --- a/power/gaia.c +++ b/power/gaia.c @@ -43,7 +43,7 @@ #define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args) /* Time necessary for the 5V and 3.3V regulator outputs to stabilize */ -#ifdef BOARD_pit +#ifdef BOARD_PIT #define DELAY_5V_SETUP (2 * MSEC) #define DELAY_3V_SETUP (2 * MSEC) #else @@ -168,7 +168,7 @@ static int wait_in_signal(enum gpio_signal signal, int value, int timeout) */ static void set_pmic_pwrok(int asserted) { -#ifdef BOARD_pit +#ifdef BOARD_PIT /* Signal is active-high */ gpio_set_level(GPIO_PMIC_PWRON, asserted); #else @@ -320,7 +320,7 @@ static int gaia_power_init(void) auto_power_on = 1; } -#ifdef BOARD_pit +#ifdef BOARD_PIT /* * Force the AP into reset unless we're doing a sysjump. Otherwise a * suspended AP may still be in a strange state from the last reboot, @@ -408,7 +408,7 @@ void chipset_force_shutdown(void) gpio_set_level(GPIO_EN_PP5000, 0); #endif -#ifdef BOARD_pit +#ifdef BOARD_PIT /* * Force the AP into reset. Otherwise it will hold XPSHOLD for a long * time if it's in a low power state. See crosbug.com/p/22233. @@ -479,7 +479,7 @@ static int power_on(void) usleep(DELAY_5V_SETUP); #endif -#ifdef BOARD_pit +#ifdef BOARD_PIT /* * 3.3V rail must come up right after 5V, because it sources power to * various buck supplies. diff --git a/power/tegra.c b/power/tegra.c index f2f38e123b..c808b494d6 100644 --- a/power/tegra.c +++ b/power/tegra.c @@ -521,7 +521,7 @@ static int react_to_xpshold(unsigned int timeout_us) /* wait for Power button release */ wait_in_signal(GPIO_SOC1V8_XPSHOLD, 1, timeout_us); -#ifdef BOARD_nyan +#ifdef BOARD_NYAN /* * nyan's GPIO_SOC1V8_XPSHOLD will go low for about 20ms after initial * high. Wait XPSHOLD_DEBOUNCE time, then check the signal again. diff --git a/test/stress.c b/test/stress.c index 31e3677c95..36afd5a587 100644 --- a/test/stress.c +++ b/test/stress.c @@ -31,23 +31,23 @@ struct i2c_test_param_t { int offset; int data; /* Non-negative represents data to write. -1 to read. */ } i2c_test_params[] = { -#ifdef BOARD_spring +#ifdef BOARD_SPRING {8, 0, 0x60, 0x0, -1}, {8, 0, 0x60, 0x0, 0x40}, {8, 0, 0x4a, 0x1, -1}, -#elif defined(BOARD_link) +#elif defined(BOARD_LINK) {8, 0, 0x16, 0x8, -1}, {8, 0, 0x16, 0x9, -1}, {8, 0, 0x16, 0xa, -1}, -#elif defined(BOARD_pit) +#elif defined(BOARD_PIT) {8, 0, 0x90, 0x19, -1}, -#elif defined(BOARD_snow) +#elif defined(BOARD_SNOW) {8, 1, 0x90, 0x19, -1}, #endif }; /* Disable I2C test for boards without test configuration */ -#if defined(BOARD_bds) || defined(BOARD_mccroskey) || \ - defined(BOARD_falco) || defined(BOARD_peppy) || defined(BOARD_wolf) +#if defined(BOARD_BDS) || defined(BOARD_MCCROSKEY) || \ + defined(BOARD_FALCO) || defined(BOARD_PEPPY) #undef CONFIG_I2C #endif diff --git a/test/test_config.h b/test/test_config.h index 055a0b60df..70a3ec72a3 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -8,33 +8,33 @@ #ifndef __CROS_EC_TEST_CONFIG_H #define __CROS_EC_TEST_CONFIG_H -#ifdef TEST_adapter +#ifdef TEST_ADAPTER #define CONFIG_CHIPSET_CAN_THROTTLE #define CONFIG_EXTPOWER_FALCO #endif -#ifdef TEST_bklight_lid +#ifdef TEST_BKLIGHT_LID #define CONFIG_BACKLIGHT_LID #endif -#ifdef TEST_bklight_passthru +#ifdef TEST_BKLIGHT_PASSTHRU #define CONFIG_BACKLIGHT_LID #define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN #endif -#ifdef TEST_kb_8042 +#ifdef TEST_KB_8042 #define CONFIG_KEYBOARD_PROTOCOL_8042 #endif -#ifdef TEST_kb_mkbp +#ifdef TEST_KB_MKBP #define CONFIG_KEYBOARD_PROTOCOL_MKBP #endif -#ifdef TEST_kb_scan +#ifdef TEST_KB_SCAN #define CONFIG_KEYBOARD_PROTOCOL_MKBP #endif -#ifdef TEST_led_spring +#ifdef TEST_LED_SPRING #define CONFIG_BATTERY_MOCK #define CONFIG_BATTERY_SMART #define CONFIG_CHARGER_INPUT_CURRENT 4032 @@ -44,7 +44,7 @@ #define I2C_PORT_CHARGER 1 #endif -#ifdef TEST_sbs_charging +#ifdef TEST_SBS_CHARGING #define CONFIG_BATTERY_MOCK #define CONFIG_BATTERY_SMART #define CONFIG_CHARGER @@ -56,13 +56,13 @@ int board_discharge_on_ac(int enabled); #define I2C_PORT_CHARGER 1 #endif -#ifdef TEST_thermal +#ifdef TEST_THERMAL #define CONFIG_CHIPSET_CAN_THROTTLE #define CONFIG_FANS 1 #define CONFIG_TEMP_SENSOR #endif -#ifdef TEST_thermal_falco +#ifdef TEST_THERMAL_FALCO #define CONFIG_BATTERY_MOCK #define CONFIG_BATTERY_SMART #define CONFIG_CHARGER -- cgit v1.2.1