From 0776ebfbbfd016bdbe0bb8e46af0659b13e52ab9 Mon Sep 17 00:00:00 2001 From: Jonathan Brandmeyer Date: Tue, 5 Jun 2018 09:37:22 -0600 Subject: stoney: Rename GPIO_PCH_RCIN_L to GPIO_SYS_RESET_L Pin rename only; no functional changes. See also b/72426192 for earlier functional changes. BUG=b:77301519 TEST=make -j buildall BRANCH=none Change-Id: I18e71118e584a5b36ba001bac24951929d2c93ff Signed-off-by: Jonathan Brandmeyer Reviewed-on: https://chromium-review.googlesource.com/1087207 Reviewed-by: Edward Hill --- board/careena/gpio.inc | 2 +- board/grunt/gpio.inc | 2 +- board/kahlee/gpio.inc | 2 +- power/stoney.c | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc index 46428ae409..58a57d5249 100644 --- a/board/careena/gpio.inc +++ b/board/careena/gpio.inc @@ -31,7 +31,7 @@ GPIO(ENABLE_BACKLIGHT_L, PIN(D, 3), GPIO_OUT_HIGH) /* Enable Backlight */ GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power Button to SOC */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_OUT_HIGH) /* Wake SOC */ -GPIO(PCH_RCIN_L, PIN(3, 5), GPIO_ODR_HIGH) /* Cold Reset to SOC */ +GPIO(SYS_RESET_L, PIN(3, 5), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) /* Case Closed Debug Mode */ GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC Entering RW */ GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP) /* Battery Present */ diff --git a/board/grunt/gpio.inc b/board/grunt/gpio.inc index 8f81a05114..ac945f4658 100644 --- a/board/grunt/gpio.inc +++ b/board/grunt/gpio.inc @@ -32,7 +32,7 @@ GPIO(ENABLE_BACKLIGHT_L, PIN(D, 3), GPIO_OUT_HIGH) /* Enable Backlight */ GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power Button to SOC */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_OUT_HIGH) /* Wake SOC */ -GPIO(PCH_RCIN_L, PIN(0, 2), GPIO_ODR_HIGH) /* Cold Reset to SOC */ +GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) /* Case Closed Debug Mode */ GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC Entering RW */ GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP) /* Battery Present */ diff --git a/board/kahlee/gpio.inc b/board/kahlee/gpio.inc index d2ba8da802..ca4fa70e92 100644 --- a/board/kahlee/gpio.inc +++ b/board/kahlee/gpio.inc @@ -86,7 +86,7 @@ GPIO(USB_C1_HPD_ODL, PIN(9, 5), GPIO_INPUT) * be used. Set as input for now, we'll set it as an output when we want to use * it. Has external pull-down resistor. */ GPIO(EC_PCH_RTCRST, PIN(B, 7), GPIO_INPUT) -GPIO(PCH_RCIN_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(USB_A_CHARGE_EN_L, PIN(3, 6), GPIO_OUT_LOW) GPIO(USB1_ENABLE, PIN(4, 1), GPIO_OUT_LOW) diff --git a/power/stoney.c b/power/stoney.c index ebbfa85698..8ebf2f168b 100644 --- a/power/stoney.c +++ b/power/stoney.c @@ -63,9 +63,9 @@ void chipset_reset(void) /* * Send a pulse to SYS_RST to trigger a warm reset. */ - gpio_set_level(GPIO_PCH_RCIN_L, 0); + gpio_set_level(GPIO_SYS_RESET_L, 0); usleep(32 * MSEC); - gpio_set_level(GPIO_PCH_RCIN_L, 1); + gpio_set_level(GPIO_SYS_RESET_L, 1); } void chipset_throttle_cpu(int throttle) -- cgit v1.2.1