From 0f250d89b91db41b9045053e8e1417a99fd6dfeb Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Wed, 14 Oct 2015 17:22:17 -0700 Subject: stm32: i2c: Add timings for 8MHz i2cclk Use the datasheet-specified 8MHz i2c timings, which are different from the 48MHz timings. BUG=chrome-os-partner:46188 BRANCH=None TEST=Probe glados_pd i2c signals, verify that clock isn't stretched ~2us on every bit received by slave. Change-Id: Id6a07bc364163c2efc61c3115043f48a79027010 Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/305714 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Alec Berg (cherry picked from commit db77cafb3e254e95139949d5931554dd4a4d9f0c) Reviewed-on: https://chromium-review.googlesource.com/310030 Reviewed-by: Gwendal Grignou Commit-Queue: Gwendal Grignou Tested-by: Gwendal Grignou --- chip/stm32/i2c-stm32f0.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/chip/stm32/i2c-stm32f0.c b/chip/stm32/i2c-stm32f0.c index 4d2da2a353..14b52770c8 100644 --- a/chip/stm32/i2c-stm32f0.c +++ b/chip/stm32/i2c-stm32f0.c @@ -68,6 +68,20 @@ static int wait_isr(int port, int mask) return EC_ERROR_TIMEOUT; } +#if defined(CONFIG_HOSTCMD_I2C_SLAVE_ADDR) && \ +defined(CONFIG_LOW_POWER_IDLE) && \ +(I2C_PORT_EC == STM32_I2C1_PORT) +/* 8MHz i2cclk register settings */ +#define STM32_I2C_TIMINGR_1000MHZ 0x00100306 +#define STM32_I2C_TIMINGR_400MHZ 0x00310309 +#define STM32_I2C_TIMINGR_100MHZ 0x10420f13 +#else +/* 48MHz i2cclk register settings */ +#define STM32_I2C_TIMINGR_1000MHZ 0x50100103 +#define STM32_I2C_TIMINGR_400MHZ 0x50330309 +#define STM32_I2C_TIMINGR_100MHZ 0xB0421214 +#endif + static void i2c_set_freq_port(const struct i2c_port_t *p) { int port = p->port; @@ -78,17 +92,17 @@ static void i2c_set_freq_port(const struct i2c_port_t *p) /* Set clock frequency */ switch (p->kbps) { case 1000: - STM32_I2C_TIMINGR(port) = 0x50100103; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_1000MHZ; break; case 400: - STM32_I2C_TIMINGR(port) = 0x50330309; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_400MHZ; break; case 100: - STM32_I2C_TIMINGR(port) = 0xB0421214; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_100MHZ; break; default: /* unknown speed, defaults to 100kBps */ CPRINTS("I2C bad speed %d kBps", p->kbps); - STM32_I2C_TIMINGR(port) = 0xB0421214; + STM32_I2C_TIMINGR(port) = STM32_I2C_TIMINGR_100MHZ; } /* Enable port */ STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; -- cgit v1.2.1