From 16c9d6d25326a011b518753cf40a782c738391a1 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Thu, 6 Dec 2018 14:41:16 -0800 Subject: atlas: enable active discharge on all rails this enables active discharge on all 12 power rails controlled by the ROHM ROP PMIC. BUG=b:120619543 BRANCH=none TEST=discharge behavior verified by sajedfarzam@ Change-Id: I842dbdcc1eab596230e12130dca272a1f449e268 Signed-off-by: Caveh Jalali Reviewed-on: https://chromium-review.googlesource.com/1371226 Commit-Ready: caveh jalali Tested-by: caveh jalali Reviewed-by: Aseda Aboagye --- board/atlas/board.c | 24 ++++++++++++++++++++---- driver/pmic_bd99992gw.h | 2 ++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/board/atlas/board.c b/board/atlas/board.c index b0e945f3b8..ebd24cc503 100644 --- a/board/atlas/board.c +++ b/board/atlas/board.c @@ -396,13 +396,29 @@ static void board_pmic_init(void) if (system_jumped_to_this_image()) return; - /* DISCHGCNT2 - enable 100 ohm discharge on V5.0A, V3.3A and V1.8A */ + /* DISCHGCNT1 - enable 100 ohm discharge on VCCIO */ i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, - BD99992GW_REG_DISCHGCNT2, 0x45); + BD99992GW_REG_DISCHGCNT1, 0x01); - /* DISCHGCNT3 - enable 100 ohm discharge on V1.00A */ + /* + * DISCHGCNT2 - enable 100 ohm discharge on + * V5.0A, V3.3DSW, V3.3A and V1.8A + */ + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_DISCHGCNT2, 0x55); + + /* + * DISCHGCNT3 - enable 500 ohm discharge on + * V1.8U_2.5U + * DISCHGCNT3 - enable 100 ohm discharge on + * V12U, V1.00A, V0.85A + */ + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_DISCHGCNT3, 0xd5); + + /* DISCHGCNT4 - enable 100 ohm discharge on V33S, V18S, V100S */ i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, - BD99992GW_REG_DISCHGCNT3, 0x04); + BD99992GW_REG_DISCHGCNT4, 0x15); /* VRMODECTRL - disable low-power mode for all rails */ i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h index 9275e3818f..db259a7b18 100644 --- a/driver/pmic_bd99992gw.h +++ b/driver/pmic_bd99992gw.h @@ -20,8 +20,10 @@ #define BD99992GW_REG_V100ACNT 0x37 #define BD99992GW_REG_V085ACNT 0x38 #define BD99992GW_REG_VRMODECTRL 0x3b +#define BD99992GW_REG_DISCHGCNT1 0x3c #define BD99992GW_REG_DISCHGCNT2 0x3d #define BD99992GW_REG_DISCHGCNT3 0x3e +#define BD99992GW_REG_DISCHGCNT4 0x3f #define BD99992GW_REG_SDWNCTRL 0x49 #define BD99992GW_SDWNCTRL_SWDN (1 << 0) /* SWDN mask */ -- cgit v1.2.1