From 192806b8da1b8714f6bfcdc548a7e8e7866b8384 Mon Sep 17 00:00:00 2001 From: Archana Patni Date: Tue, 2 Feb 2016 19:29:05 +0530 Subject: skylake: set and clear wake masks in S0 <-> S0ix transitions In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the wake masks when the SMI is invoked. For S0ix, EC sets and clears the wake mask via this patch. These functions are directly invoked from the state machine transition states. During S0ix entry, the wake mask for lid open is enabled. During S0ix exit, the wake mask for lid open is cleared. All pending events are also cleared BRANCH=none BUG=chrome-os-partner:48834 TEST=test lidopen in S0ix Signed-off-by: Archana Patni Signed-off-by: Subramony Sesha Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f Reviewed-on: https://chromium-review.googlesource.com/320190 Commit-Ready: Divya Jyothi Tested-by: Divya Jyothi Reviewed-by: Shawn N --- chip/mec1322/lpc.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/lpc.h | 3 +++ power/skylake.c | 5 +++++ 3 files changed, 56 insertions(+) diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index fe082d51ea..a53a02efad 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -18,6 +18,7 @@ #include "task.h" #include "timer.h" #include "util.h" +#include "chipset.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_LPC, outstr) @@ -609,3 +610,50 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) DECLARE_HOST_COMMAND(EC_CMD_GET_PROTOCOL_INFO, lpc_get_protocol_info, EC_VER_MASK(0)); + +#ifdef CONFIG_POWER_S0IX +static void lpc_clear_host_events(void) +{ + while (lpc_query_host_event_state() != 0); +} + +/* + * In AP S0 -> S3 & S0ix transitions, + * the chipset_suspend is called. + * + * The chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON) + * is used to detect the S0ix transiton. + * + * During S0ix entry, the wake mask for lid open is enabled. + * + */ +void lpc_enable_wake_mask_for_lid_open(void) +{ + if ((chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) || + chipset_in_state(CHIPSET_STATE_STANDBY)) { + uint32_t mask = 0; + + mask = ((lpc_get_host_event_mask(LPC_HOST_EVENT_WAKE)) | + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)); + + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, mask); +} } + +/* + * In AP S0ix & S3 -> S0 transitions, + * the chipset_resume hook is called. + * + * During S0ix exit, the wake mask for lid open is disabled. + * All pending events are cleared + * + */ +void lpc_disable_wake_mask_for_lid_open(void) +{ + if ((chipset_in_state(CHIPSET_STATE_STANDBY | CHIPSET_STATE_ON)) || + chipset_in_state(CHIPSET_STATE_ON)) { + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); + lpc_clear_host_events(); + } +} + +#endif diff --git a/include/lpc.h b/include/lpc.h index c90a54a71c..3b77736f00 100644 --- a/include/lpc.h +++ b/include/lpc.h @@ -120,4 +120,7 @@ void lpc_disable_acpi_interrupts(void); /* Enable LPC ACPI interrupts */ void lpc_enable_acpi_interrupts(void); +void lpc_enable_wake_mask_for_lid_open(void); + +void lpc_disable_wake_mask_for_lid_open(void); #endif /* __CROS_EC_LPC_H */ diff --git a/power/skylake.c b/power/skylake.c index d19a639f77..9b3b74c4bf 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -17,6 +17,7 @@ #include "task.h" #include "util.h" #include "wireless.h" +#include "lpc.h" /* Console output macros */ #define CPUTS(outstr) cputs(CC_CHIPSET, outstr) @@ -351,6 +352,8 @@ static enum power_state _power_handle_state(enum power_state state) /* call hooks before standby */ hook_notify(HOOK_CHIPSET_SUSPEND); + lpc_enable_wake_mask_for_lid_open(); + /* * Enable idle task deep sleep. Allow the low power idle task * to go into deep sleep in S0ix. @@ -361,6 +364,8 @@ static enum power_state _power_handle_state(enum power_state state) case POWER_S0ixS0: + lpc_disable_wake_mask_for_lid_open(); + /* Call hooks now that rails are up */ hook_notify(HOOK_CHIPSET_RESUME); -- cgit v1.2.1