From 24c077476d8263d9257b5840d4e502d5692c8b73 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 30 Apr 2018 19:10:49 -0700 Subject: yorp: Control backlight based on chipset transitions This change enables/disables backlight based on the chipset state transition. BUG=b:78897667 BRANCH=None TEST=None Change-Id: I4da331cb94f7a304a76fce93b73c38016f5b0f4d Signed-off-by: Furquan Shaikh Reviewed-on: https://chromium-review.googlesource.com/1036798 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin Reviewed-by: Jett Rink Reviewed-by: Justin TerAvest --- board/yorp/board.c | 12 ++++++++++++ board/yorp/gpio.inc | 1 + 2 files changed, 13 insertions(+) diff --git a/board/yorp/board.c b/board/yorp/board.c index 133e0da19f..d573571aff 100644 --- a/board/yorp/board.c +++ b/board/yorp/board.c @@ -213,6 +213,12 @@ static void board_chipset_resume(void) { /* Enable Trackpad Power when chipset is in S0 */ gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 0); + + /* + * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and + * LID_OPEN connection in hardware. + */ + gpio_set_level(GPIO_ENABLE_BACKLIGHT, 1); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_chipset_resume, HOOK_PRIO_DEFAULT); @@ -221,6 +227,12 @@ static void board_chipset_suspend(void) { /* Disable Trackpad Power when chipset transitions to sleep state */ gpio_set_level(GPIO_EN_P3300_TRACKPAD_ODL, 1); + + /* + * GPIO_ENABLE_BACKLIGHT is AND'ed with SOC_EDP_BKLTEN from the SoC and + * LID_OPEN connection in hardware. + */ + gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0); } DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, board_chipset_suspend, HOOK_PRIO_DEFAULT); diff --git a/board/yorp/gpio.inc b/board/yorp/gpio.inc index 83c83a731b..bd503be07e 100644 --- a/board/yorp/gpio.inc +++ b/board/yorp/gpio.inc @@ -59,6 +59,7 @@ GPIO(PP3300_PG, PIN(6, 0), GPIO_INPUT) /* PP3300_PG_OD */ GPIO(PMIC_EN, PIN(7, 2), GPIO_OUT_LOW) /* Enable A Rails via PMIC */ GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC. All _A rails now up. */ GPIO(PCH_SYS_PWROK, PIN(B, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK. All S0 rails now up. */ +GPIO(ENABLE_BACKLIGHT, PIN(D, 3), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD */ GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT) -- cgit v1.2.1