From 2d25b40b758445fa29fa003534817acc1244e132 Mon Sep 17 00:00:00 2001 From: Alexandru M Stan Date: Tue, 16 Dec 2014 15:23:57 -0800 Subject: cortex-m0: NVIC: Fix macro for the priority registers We actually need to care about x, the PRI register is actually a list of registers (and we have code that uses some of the later ones). BUG=None, discovered while chrome-os-partner:33451 TEST=Change priorities of irqs(like UART over GPIO(spi_event)), note how they actually work and override each other as told BRANCH=None Change-Id: I9f5bf7ba9d4211f782ff260fbce17deb7c53a31f Signed-off-by: Alexandru M Stan Reviewed-on: https://chromium-review.googlesource.com/236087 Reviewed-by: Vincent Palatin Reviewed-by: Alec Berg Reviewed-by: Randall Spangler --- core/cortex-m0/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h index 8b874d9688..52e46551b0 100644 --- a/core/cortex-m0/cpu.h +++ b/core/cortex-m0/cpu.h @@ -18,7 +18,7 @@ #define CPU_NVIC_DIS(x) CPUREG(0xe000e180) #define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) #define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) -#define CPU_NVIC_PRI(x) CPUREG(0xe000e400) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400 + 4 * (x)) /* System Control Block */ -- cgit v1.2.1