From 35f64509fc74a99c147249fd06392d9c3abdc807 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Tue, 22 Jan 2019 13:15:50 +0800 Subject: it83xx: add enable/disable espi pad function We can call this function to enable/disable espi pad if needed. BUG=b:121105042 BRANCH=none TEST=buildall Change-Id: I61561b1a4657947e27053de3e8b2ef053651d949 Signed-off-by: Dino Li Reviewed-on: https://chromium-review.googlesource.com/1426303 Commit-Ready: Justin TerAvest Tested-by: Justin TerAvest Reviewed-by: Jett Rink --- chip/it83xx/clock.c | 8 ++++---- chip/it83xx/espi.c | 13 +++++++++++++ chip/it83xx/intc.h | 1 + 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index bb211352df..75c4e1dbeb 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -205,7 +205,7 @@ static void clock_set_pll(enum pll_freq_idx idx) * On DX version, we have to disable eSPI pad before changing * PLL sequence or sequence will fail if CS# pin is low. */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 6); + espi_enable_pad(0); #endif #endif /* Update PLL settings. */ @@ -213,7 +213,7 @@ static void clock_set_pll(enum pll_freq_idx idx) #ifdef CONFIG_HOSTCMD_ESPI #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED /* Enable eSPI pad after changing PLL sequence. */ - IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); + espi_enable_pad(1); #endif /* (b:70537592) Change back to ESPI CS# function. */ IT83XX_GPIO_GPCRM5 &= ~0xc0; @@ -450,7 +450,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds) #if defined(IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED) && \ defined(CONFIG_HOSTCMD_ESPI) /* Disable eSPI pad. */ - IT83XX_ESPI_ESGCTRL2 |= (1 << 6); + espi_enable_pad(0); #endif clock_ec_pll_ctrl(EC_PLL_SLEEP); interrupt_enable(); @@ -480,7 +480,7 @@ defined(CONFIG_HOSTCMD_ESPI) * setting is the same, so the operation of enabling eSPI pad we * added in clock_set_pll() will not be applied. */ - IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); + espi_enable_pad(1); #endif system_reset(SYSTEM_RESET_HARD); } diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index c600f02317..21e462596b 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -569,6 +569,19 @@ void espi_interrupt(void) task_clear_pending_irq(IT83XX_IRQ_ESPI); } +#ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED +/* Enable/Disable eSPI pad */ +void espi_enable_pad(int enable) +{ + if (enable) + /* Enable eSPI pad. */ + IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6); + else + /* Disable eSPI pad. */ + IT83XX_ESPI_ESGCTRL2 |= (1 << 6); +} +#endif + void espi_init(void) { /* diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h index 9fa6341953..2655f64b45 100644 --- a/chip/it83xx/intc.h +++ b/chip/it83xx/intc.h @@ -25,6 +25,7 @@ void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); void espi_fw_reset_module(void); void espi_interrupt(void); void espi_vw_interrupt(void); +void espi_enable_pad(int enable); void espi_init(void); #if defined(CONFIG_HOSTCMD_X86) && defined(HAS_TASK_KEYPROTO) -- cgit v1.2.1