From 363e056db24c5ccb4ca80a83ab212281e02a0580 Mon Sep 17 00:00:00 2001 From: tim Date: Tue, 11 Dec 2018 18:40:52 +0800 Subject: it83xx/spi: rename spi.c to spi_master.c In it83xx chip, the file of spi.c is renamed to spi_master.c, and the related config is renamed too. BUG=none BRANCH=none TEST=none Change-Id: Ia696e62afa2ff06da68a3e4af685615b1dbcc8e9 Signed-off-by: tim Reviewed-on: https://chromium-review.googlesource.com/1372870 Commit-Ready: ChromeOS CL Exonerator Bot Tested-by: Tim2 Lin Reviewed-by: Jett Rink --- board/it83xx_evb/board.h | 2 +- chip/it83xx/build.mk | 2 +- chip/it83xx/spi.c | 171 ----------------------------------------------- chip/it83xx/spi_master.c | 171 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 173 insertions(+), 173 deletions(-) delete mode 100644 chip/it83xx/spi.c create mode 100644 chip/it83xx/spi_master.c diff --git a/board/it83xx_evb/board.h b/board/it83xx_evb/board.h index b018fb65c6..379362d4c5 100644 --- a/board/it83xx_evb/board.h +++ b/board/it83xx_evb/board.h @@ -28,7 +28,7 @@ #define CONFIG_POWER_BUTTON #define CONFIG_PWM /* Use CS0 of SSPI */ -#define CONFIG_SPI +#define CONFIG_SPI_MASTER #define CONFIG_SPI_FLASH_PORT 0 #define CONFIG_UART_HOST #define CONFIG_HOSTCMD_LPC diff --git a/chip/it83xx/build.mk b/chip/it83xx/build.mk index 2d664669f7..365a993113 100644 --- a/chip/it83xx/build.mk +++ b/chip/it83xx/build.mk @@ -21,7 +21,7 @@ chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_HOSTCMD_X86)+=lpc.o ec2i.o chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o -chip-$(CONFIG_SPI)+=spi.o +chip-$(CONFIG_SPI_MASTER)+=spi_master.o chip-$(CONFIG_PECI)+=peci.o chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o chip-$(CONFIG_I2C)+=i2c.o diff --git a/chip/it83xx/spi.c b/chip/it83xx/spi.c deleted file mode 100644 index 1337f7ccac..0000000000 --- a/chip/it83xx/spi.c +++ /dev/null @@ -1,171 +0,0 @@ -/* Copyright 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* SPI module for Chrome EC */ - -#include "clock.h" -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "spi.h" -#include "task.h" -#include "timer.h" -#include "util.h" - -/* Console output macros */ -#define CPUTS(outstr) cputs(CC_SPI, outstr) -#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) - -enum sspi_clk_sel { - sspi_clk_24mhz = 0, - sspi_clk_12mhz, - sspi_clk_8mhz, - sspi_clk_6mhz, - sspi_clk_4p8mhz, - sspi_clk_4mhz, - sspi_clk_3p428mhz, - sspi_clk_3mhz, -}; - -enum sspi_ch_sel { - SSPI_CH_CS0 = 0, - SSPI_CH_CS1, -}; - -static void sspi_frequency(enum sspi_clk_sel freq) -{ - /* - * bit[6:5] - * Bit 6:Clock Polarity (CLPOL) - * 0: SSCK is low in the idle mode. - * 1: SSCK is high in the idle mode. - * Bit 5:Clock Phase (CLPHS) - * 0: Latch data on the first SSCK edge. - * 1: Latch data on the second SSCK edge. - * - * bit[4:2] - * 000b: 1/2 clk_sspi - * 001b: 1/4 clk_sspi - * 010b: 1/6 clk_sspi - * 011b: 1/8 clk_sspi - * 100b: 1/10 clk_sspi - * 101b: 1/12 clk_sspi - * 110b: 1/14 clk_sspi - * 111b: 1/16 clk_sspi - * - * SSCK frequency is [freq] MHz and mode 3. - * note, clk_sspi need equal to 48MHz above. - */ - IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2)); -} - -static void sspi_transmission_end(void) -{ - /* Write 1 to end the SPI transmission. */ - IT83XX_SSPI_SPISTS = 0x20; - - /* Short delay for "Transfer End Flag" */ - IT83XX_GCTRL_WNCKR = 0; - - /* Write 1 to clear this bit and terminate data transmission. */ - IT83XX_SSPI_SPISTS = 0x02; -} - -/* We assume only one SPI port in the chip, one SPI device */ -int spi_enable(int port, int enable) -{ - if (enable) { - /* - * bit[5:4] - * 00b: SPI channel 0 and channel 1 are disabled. - * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled. - * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled. - * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled. - */ - if (port == SSPI_CH_CS1) - IT83XX_GPIO_GRC1 |= 0x20; - else - IT83XX_GPIO_GRC1 |= 0x10; - - gpio_config_module(MODULE_SPI, 1); - } else { - if (port == SSPI_CH_CS1) - IT83XX_GPIO_GRC1 &= ~0x20; - else - IT83XX_GPIO_GRC1 &= ~0x10; - - gpio_config_module(MODULE_SPI, 0); - } - - return EC_SUCCESS; -} - -int spi_transaction(const struct spi_device_t *spi_device, - const uint8_t *txdata, int txlen, - uint8_t *rxdata, int rxlen) -{ - int idx; - uint8_t port = spi_device->port; - static struct mutex spi_mutex; - - mutex_lock(&spi_mutex); - /* bit[0]: Write cycle */ - IT83XX_SSPI_SPICTRL2 &= ~0x04; - for (idx = 0x00; idx < txlen; idx++) { - IT83XX_SSPI_SPIDATA = txdata[idx]; - if (port == SSPI_CH_CS1) - /* Write 1 to start the data transmission of CS1 */ - IT83XX_SSPI_SPISTS |= 0x08; - else - /* Write 1 to start the data transmission of CS0 */ - IT83XX_SSPI_SPISTS |= 0x10; - } - - /* bit[1]: Read cycle */ - IT83XX_SSPI_SPICTRL2 |= 0x04; - for (idx = 0x00; idx < rxlen; idx++) { - if (port == SSPI_CH_CS1) - /* Write 1 to start the data transmission of CS1 */ - IT83XX_SSPI_SPISTS |= 0x08; - else - /* Write 1 to start the data transmission of CS0 */ - IT83XX_SSPI_SPISTS |= 0x10; - rxdata[idx] = IT83XX_SSPI_SPIDATA; - } - - sspi_transmission_end(); - mutex_unlock(&spi_mutex); - - return EC_SUCCESS; -} - -static void sspi_init(void) -{ - int i; - - clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0); - sspi_frequency(sspi_clk_8mhz); - - /* - * bit[5:3] Byte Width (BYTEWIDTH) - * 000b: 8-bit transmission - * 001b: 1-bit transmission - * 010b: 2-bit transmission - * 011b: 3-bit transmission - * 100b: 4-bit transmission - * 101b: 5-bit transmission - * 110b: 6-bit transmission - * 111b: 7-bit transmission - * - * bit[1] Blocking selection - */ - IT83XX_SSPI_SPICTRL2 |= 0x02; - - for (i = 0; i < spi_devices_used; i++) - /* Disabling spi module */ - spi_enable(spi_devices[i].port, 0); -} -DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI); diff --git a/chip/it83xx/spi_master.c b/chip/it83xx/spi_master.c new file mode 100644 index 0000000000..1337f7ccac --- /dev/null +++ b/chip/it83xx/spi_master.c @@ -0,0 +1,171 @@ +/* Copyright 2015 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* SPI module for Chrome EC */ + +#include "clock.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "spi.h" +#include "task.h" +#include "timer.h" +#include "util.h" + +/* Console output macros */ +#define CPUTS(outstr) cputs(CC_SPI, outstr) +#define CPRINTS(format, args...) cprints(CC_SPI, format, ## args) + +enum sspi_clk_sel { + sspi_clk_24mhz = 0, + sspi_clk_12mhz, + sspi_clk_8mhz, + sspi_clk_6mhz, + sspi_clk_4p8mhz, + sspi_clk_4mhz, + sspi_clk_3p428mhz, + sspi_clk_3mhz, +}; + +enum sspi_ch_sel { + SSPI_CH_CS0 = 0, + SSPI_CH_CS1, +}; + +static void sspi_frequency(enum sspi_clk_sel freq) +{ + /* + * bit[6:5] + * Bit 6:Clock Polarity (CLPOL) + * 0: SSCK is low in the idle mode. + * 1: SSCK is high in the idle mode. + * Bit 5:Clock Phase (CLPHS) + * 0: Latch data on the first SSCK edge. + * 1: Latch data on the second SSCK edge. + * + * bit[4:2] + * 000b: 1/2 clk_sspi + * 001b: 1/4 clk_sspi + * 010b: 1/6 clk_sspi + * 011b: 1/8 clk_sspi + * 100b: 1/10 clk_sspi + * 101b: 1/12 clk_sspi + * 110b: 1/14 clk_sspi + * 111b: 1/16 clk_sspi + * + * SSCK frequency is [freq] MHz and mode 3. + * note, clk_sspi need equal to 48MHz above. + */ + IT83XX_SSPI_SPICTRL1 |= (0x60 | (freq << 2)); +} + +static void sspi_transmission_end(void) +{ + /* Write 1 to end the SPI transmission. */ + IT83XX_SSPI_SPISTS = 0x20; + + /* Short delay for "Transfer End Flag" */ + IT83XX_GCTRL_WNCKR = 0; + + /* Write 1 to clear this bit and terminate data transmission. */ + IT83XX_SSPI_SPISTS = 0x02; +} + +/* We assume only one SPI port in the chip, one SPI device */ +int spi_enable(int port, int enable) +{ + if (enable) { + /* + * bit[5:4] + * 00b: SPI channel 0 and channel 1 are disabled. + * 10b: SSCK/SMOSI/SMISO/SSCE1# are enabled. + * 01b: SSCK/SMOSI/SMISO/SSCE0# are enabled. + * 11b: SSCK/SMOSI/SMISO/SSCE1#/SSCE0# are enabled. + */ + if (port == SSPI_CH_CS1) + IT83XX_GPIO_GRC1 |= 0x20; + else + IT83XX_GPIO_GRC1 |= 0x10; + + gpio_config_module(MODULE_SPI, 1); + } else { + if (port == SSPI_CH_CS1) + IT83XX_GPIO_GRC1 &= ~0x20; + else + IT83XX_GPIO_GRC1 &= ~0x10; + + gpio_config_module(MODULE_SPI, 0); + } + + return EC_SUCCESS; +} + +int spi_transaction(const struct spi_device_t *spi_device, + const uint8_t *txdata, int txlen, + uint8_t *rxdata, int rxlen) +{ + int idx; + uint8_t port = spi_device->port; + static struct mutex spi_mutex; + + mutex_lock(&spi_mutex); + /* bit[0]: Write cycle */ + IT83XX_SSPI_SPICTRL2 &= ~0x04; + for (idx = 0x00; idx < txlen; idx++) { + IT83XX_SSPI_SPIDATA = txdata[idx]; + if (port == SSPI_CH_CS1) + /* Write 1 to start the data transmission of CS1 */ + IT83XX_SSPI_SPISTS |= 0x08; + else + /* Write 1 to start the data transmission of CS0 */ + IT83XX_SSPI_SPISTS |= 0x10; + } + + /* bit[1]: Read cycle */ + IT83XX_SSPI_SPICTRL2 |= 0x04; + for (idx = 0x00; idx < rxlen; idx++) { + if (port == SSPI_CH_CS1) + /* Write 1 to start the data transmission of CS1 */ + IT83XX_SSPI_SPISTS |= 0x08; + else + /* Write 1 to start the data transmission of CS0 */ + IT83XX_SSPI_SPISTS |= 0x10; + rxdata[idx] = IT83XX_SSPI_SPIDATA; + } + + sspi_transmission_end(); + mutex_unlock(&spi_mutex); + + return EC_SUCCESS; +} + +static void sspi_init(void) +{ + int i; + + clock_enable_peripheral(CGC_OFFSET_SSPI, 0, 0); + sspi_frequency(sspi_clk_8mhz); + + /* + * bit[5:3] Byte Width (BYTEWIDTH) + * 000b: 8-bit transmission + * 001b: 1-bit transmission + * 010b: 2-bit transmission + * 011b: 3-bit transmission + * 100b: 4-bit transmission + * 101b: 5-bit transmission + * 110b: 6-bit transmission + * 111b: 7-bit transmission + * + * bit[1] Blocking selection + */ + IT83XX_SSPI_SPICTRL2 |= 0x02; + + for (i = 0; i < spi_devices_used; i++) + /* Disabling spi module */ + spi_enable(spi_devices[i].port, 0); +} +DECLARE_HOOK(HOOK_INIT, sspi_init, HOOK_PRIO_INIT_SPI); -- cgit v1.2.1