From 37edd51bc1465a873ede878978556542b8fe3c20 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Thu, 3 Oct 2019 12:00:17 +0800 Subject: chip/it83xx: introduction of IT83202/BX version - Changing PLL and standby instruction didn't work on AX have been fixed on this version, so we can remove patches dedicated for AX. - Enable more chip config option. - Disable IT83XX_INTC_GROUP_21_22_SUPPORT option: Because IT8xxx2 series has its own interrupt group 21 and 22, so we will create another CL to support them. - System triggers a soft reset by default if IT83XX_ETWD_HW_RESET_SUPPORT option is enabled. BUG=b:134542199; b:133460224; b:142029177 BRANCH=none TEST=boots on BX version. console command reboot: reboot hard Hard-Rebooting! [Reset cause: power-on hard] reboot Rebooting! [Reset cause: soft] Change-Id: I06e57952cd758b4f344ada0f87729c961b1e747b Signed-off-by: Dino Li Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835884 Reviewed-by: Jett Rink --- chip/it83xx/clock.c | 14 ++++---------- chip/it83xx/config_chip_it8xxx2.h | 17 ++++++++++++----- chip/it83xx/registers.h | 2 ++ chip/it83xx/system.c | 6 +++++- 4 files changed, 23 insertions(+), 16 deletions(-) diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index b3771adcb5..468037f0e9 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -193,10 +193,6 @@ static void clock_set_pll(enum pll_freq_idx idx) { int pll; - /* TODO(b/134542199): fix me... Changing PLL failed on it83202/ax */ - if (IS_ENABLED(CHIP_VARIANT_IT83202AX)) - return; - pll_div_fnd = clock_pll_ctrl[idx].div_fnd; pll_div_ec = clock_pll_ctrl[idx].div_ec; pll_div_jtag = clock_pll_ctrl[idx].div_jtag; @@ -425,13 +421,11 @@ void clock_cpu_standby(void) asm("standby wake_grant"); } else if (IS_ENABLED(CHIP_CORE_RISCV)) { /* - * An interrupt is not able to wake EC up from low power mode. - * (AX bug) + * TODO(b:142029177): we have to enable interrupts before + * standby instruction on IT8xxx2 series. */ - if (IS_ENABLED(CHIP_VARIANT_IT83202AX)) - asm("nop"); - else - asm("wfi"); + interrupt_enable(); + asm("wfi"); } } diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 0c2dbced13..deef92893d 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -26,15 +26,24 @@ #define CHIP_RAM_SPACE_RESERVED 0x3000 #define CONFIG_RAM_BASE 0x80080000 -#define CONFIG_RAM_SIZE 0x00040000 +#define CONFIG_RAM_SIZE 0x00010000 #define CONFIG_PROGRAM_MEMORY_BASE (CHIP_ILM_BASE) -#if defined(CHIP_VARIANT_IT83202AX) +#if defined(CHIP_VARIANT_IT83202BX) /* TODO(b/133460224): enable properly chip config option. */ -#define CONFIG_FLASH_SIZE 0x00040000 +#define CONFIG_FLASH_SIZE 0x00080000 /* chip id is 3 bytes */ #define IT83XX_CHIP_ID_3BYTES +/* + * Disable eSPI pad, then PLL change + * (include EC clock frequency) is succeed even CS# is low. + */ +#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED +/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */ +#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE +/* Watchdog reset supports hardware reset. */ +#define IT83XX_ETWD_HW_RESET_SUPPORT /* * More GPIOs can be set as 1.8v input. * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs. @@ -42,8 +51,6 @@ #define IT83XX_GPIO_1P8V_PIN_EXTENDED /* All GPIOs support interrupt on rising, falling, and either edge. */ #define IT83XX_GPIO_INT_FLEXIBLE -/* Enable interrupts of group 21 and 22. */ -#define IT83XX_INTC_GROUP_21_22_SUPPORT /* Enable detect type-c plug in interrupt. */ #define IT83XX_INTC_PLUG_IN_SUPPORT #else diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 52e6c3b43c..b35e36c255 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -790,6 +790,8 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) +/* bit[0] = 0 or 1 : disable or enable ETWD hardware reset */ +#define ETWD_HW_RST_EN BIT(0) #define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) #define ILMCR_ILM2_ENABLE BIT(2) #define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c index 144d75c35c..537455d4b9 100644 --- a/chip/it83xx/system.c +++ b/chip/it83xx/system.c @@ -119,6 +119,10 @@ void chip_pre_init(void) { /* bit4, enable debug mode through SMBus */ IT83XX_SMB_SLVISELR &= ~BIT(4); + + if (IS_ENABLED(IT83XX_ETWD_HW_RESET_SUPPORT)) + /* System triggers a soft reset by default (command: reboot). */ + IT83XX_GCTRL_ETWDUARTCR &= ~ETWD_HW_RST_EN; } #define BRAM_VALID_MAGIC 0x4252414D /* "BRAM" */ @@ -194,7 +198,7 @@ void system_reset(int flags) /* bit0: enable watchdog hardware reset. */ #ifdef IT83XX_ETWD_HW_RESET_SUPPORT if (flags & SYSTEM_RESET_HARD) - IT83XX_GCTRL_ETWDUARTCR |= BIT(0); + IT83XX_GCTRL_ETWDUARTCR |= ETWD_HW_RST_EN; #endif /* * Writing invalid key to watchdog module triggers a soft or hardware -- cgit v1.2.1