From 3b162523949d29d44e020daa7f613df533b9abce Mon Sep 17 00:00:00 2001 From: yoojin Date: Mon, 4 Aug 2014 14:22:06 +0900 Subject: Winky : Change power sequence for Core well stable on BYT-M Winky included PCIe device. Intel BYT-M spec. : Core well stable to DRAM_CORE_PWROK and PMC_CORE_PWROK assertion for power rails needed by PCIe devices is minimum 99ms. BUG=chrome-os-partner:31116 TEST=emerge-winky chromeos-ec Measure signal waveforms in power up sequence. Change-Id: I2afde9f1216b360c926c254f98d64124d2dbf080 Reviewed-on: https://chromium-review.googlesource.com/210952 Reviewed-by: YongBeum Ha Tested-by: YongBeum Ha Reviewed-by: Aaron Durbin Commit-Queue: YongBeum Ha --- power/baytrail.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) mode change 100644 => 100755 power/baytrail.c diff --git a/power/baytrail.c b/power/baytrail.c old mode 100644 new mode 100755 index 995889ef6b..921b642f3d --- a/power/baytrail.c +++ b/power/baytrail.c @@ -272,10 +272,10 @@ enum power_state power_handle_state(enum power_state state) disable_sleep(SLEEP_MASK_AP_RUN); /* - * Wait 15 ms after all voltages good. 100 ms is only needed - * for PCIe devices; mini-PCIe devices should need only 10 ms. + * Wait 105 ms after all voltages good. 100 ms is needed + * for PCIe devices; mini-PCIe devices is needed 10 ms. */ - msleep(15); + msleep(105); /* * Throttle CPU if necessary. This should only be asserted -- cgit v1.2.1