From 3d758ca131e71ffc8d407776255bff4b2ed3bce0 Mon Sep 17 00:00:00 2001 From: Namyoon Woo Date: Fri, 13 Dec 2019 14:20:01 -0800 Subject: add BOARD_EC_CR50_COMM_SUPPORT to board properties This CL add a board property indicating EC-CR50 communication support. The target boards are Volteer,Dedede,Puff, and Zork. It shall be detected if the H1 strap configuration value is either 0x0E or 0xE0. BUG=b:146567516, chromium:1027660 BRANCH=cr50 TEST=Flashed AP firmware through CCD on Grunt, Octopus, Scarlet and Atlas. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:2 a6:0 a12:0 [0.005886 Valid strap: 0xa properties: 0x41] > brdprop properties = 0x1141 > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600b8: DIOB3 3 IN GPIO0_GPIO2 400600c0: DIOB4 0 IN PD ... 40060100: GPIO0_GPIO2 7 DIOB3 ... 40060120: GPIO0_GPIO10 6 DIOB4 Flashed AP firmware on a reworked board with 1M ohm on DIOA1 and 5k ohm on DIOA9. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005886 Valid strap: 0xe properties: 0x200041] > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600c0: DIOB4 3 IN PD GPIO0_GPIO2 ... 40060100: GPIO0_GPIO2 6 DIOB4 ... 40060120: GPIO0_GPIO10 6 DIOB4 Change-Id: If60765190a385a0e728177911b1ec738c6a00d99 Signed-off-by: Namyoon Woo Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979612 Reviewed-by: Mary Ruthven --- board/cr50/board.c | 38 +++++++++++++++++++++++++++++++++++++- board/cr50/board.h | 2 ++ board/cr50/gpio.inc | 8 +++++--- board/cr50/scratch_reg1.h | 6 ++++++ 4 files changed, 50 insertions(+), 4 deletions(-) diff --git a/board/cr50/board.c b/board/cr50/board.c index e3d46c9e8f..2463534167 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -181,6 +181,11 @@ int board_tpm_mode_change_allowed(void) return !!(board_properties & BOARD_ALLOW_CHANGE_TPM_MODE); } +int board_has_ec_cr50_comm_support(void) +{ + return !!(board_properties & BOARD_EC_CR50_COMM_SUPPORT); +} + /* Get header address of the backup RW copy. */ const struct SignedHeader *get_other_rw_addr(void) { @@ -294,7 +299,18 @@ static struct board_cfg board_cfg_table[] = { BOARD_CLOSED_SOURCE_SET1 | BOARD_NO_INA_SUPPORT | BOARD_ALLOW_CHANGE_TPM_MODE, }, - + /* Dedede/Puff/Volteer: DIOA9 = 5K PU, DIOA1 = 1M PU */ + { + .strap_cfg = 0x0E, + .board_properties = BOARD_SLAVE_CONFIG_SPI | + BOARD_USE_PLT_RESET | BOARD_EC_CR50_COMM_SUPPORT, + }, + /* Zork: DIOA12 = 5K PU, DIOA6 = 1M PU */ + { + .strap_cfg = 0xE0, + .board_properties = BOARD_SLAVE_CONFIG_I2C | + BOARD_USE_PLT_RESET | BOARD_EC_CR50_COMM_SUPPORT, + }, }; void post_reboot_request(void) @@ -644,6 +660,26 @@ static void configure_board_specific_gpios(void) if (board_uses_closed_source_set1()) closed_source_set1_configure_gpios(); + + /* + * Connect GPIO_AP_FLASH_SELECT, which is GPIO(0, 2) to DIOB4 if EC-CR50 + * commnuication is supported. Otherwise, connect it to DIOB3. + */ + if (board_has_ec_cr50_comm_support()) { + /* Connect GPIO_AP_FLASH_SELECT to DIOB4. */ + GWRITE(PINMUX, DIOB4_SEL, GC_PINMUX_GPIO0_GPIO2_SEL); + GWRITE(PINMUX, GPIO0_GPIO2_SEL, GC_PINMUX_DIOB4_SEL); + + /* Enable the input */ + GWRITE_FIELD(PINMUX, DIOB4_CTL, IE, 1); + } else { + /* Connect GPIO_AP_FLASH_SELECT to DIOB3. */ + GWRITE(PINMUX, DIOB3_SEL, GC_PINMUX_GPIO0_GPIO2_SEL); + GWRITE(PINMUX, GPIO0_GPIO2_SEL, GC_PINMUX_DIOB3_SEL); + + /* Enable the input */ + GWRITE_FIELD(PINMUX, DIOB3_CTL, IE, 1); + } } static uint8_t mismatched_board_id; diff --git a/board/cr50/board.h b/board/cr50/board.h index 12b2e72a1b..43bc6abd78 100644 --- a/board/cr50/board.h +++ b/board/cr50/board.h @@ -320,6 +320,8 @@ int board_uses_closed_loop_reset(void); int board_has_ina_support(void); /* The board allows vendor commands to enable/disable tpm. */ int board_tpm_mode_change_allowed(void); +/* The board supports EC-CR50 communication. */ +int board_has_ec_cr50_comm_support(void); int board_id_is_mismatched(void); /* Allow for deep sleep to be enabled on AP shutdown */ int board_deep_sleep_allowed(void); diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc index 73a7360de1..76d6adf0f1 100644 --- a/board/cr50/gpio.inc +++ b/board/cr50/gpio.inc @@ -123,6 +123,10 @@ GPIO(INT_AP_L, PIN(0, 0), GPIO_OUT_HIGH) /* Use these to take over the AP & EC flash (only when AP & EC are off!) */ GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW) +/* + * If this gpio is changed, you must update the AP_FLASH_SELECT pinmux + * setup in board.c accordingly. + */ GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW) /* @@ -207,10 +211,8 @@ UNIMPLEMENTED(ENTERING_RW) #endif /* GPIOs - mark outputs as inputs too, to read back from the driven pad */ -PINMUX(GPIO(INT_AP_L), A5, DIO_INPUT) /* DIOB7 is p_digitial_od */ - /* We can't pull it up */ +PINMUX(GPIO(INT_AP_L), A5, DIO_INPUT) PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT) -PINMUX(GPIO(AP_FLASH_SELECT), B3, DIO_INPUT) PINMUX(GPIO(MONITOR_I2CS_SDA), A1, GPIO_INPUT) /* diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h index 79eb4b4382..ac98d98883 100644 --- a/board/cr50/scratch_reg1.h +++ b/board/cr50/scratch_reg1.h @@ -85,6 +85,11 @@ */ #define BOARD_ALLOW_CHANGE_TPM_MODE BIT(20) +/* + * The board supports EC-CR50 communication. + */ +#define BOARD_EC_CR50_COMM_SUPPORT BIT(21) + /* * Macro to capture all properties related to board strapping pins. This must be * updated if additional strap related properties are added. @@ -95,6 +100,7 @@ BOARD_CLOSED_SOURCE_SET1 | \ BOARD_DEEP_SLEEP_DISABLED | \ BOARD_DETECT_AP_WITH_UART | \ + BOARD_EC_CR50_COMM_SUPPORT | \ BOARD_NEEDS_SYS_RST_PULL_UP | \ BOARD_NO_INA_SUPPORT | \ BOARD_SLAVE_CONFIG_I2C | \ -- cgit v1.2.1