From 47de1e86750736f6e410e359b8f5980811be3556 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Thu, 28 Jun 2018 19:35:32 -0700 Subject: npcx7: system: change the default value of FMUL_WIN_DLY This CL changes the default value of Nuvoton internal register, FMUL_WIN_DLY, from 0x8A to 0x81 on npcx7 ec series. It increases the tuning rate of the FMULs to improve audio quality. For consistency, this is done across all NPCX7 devices. BRANCH=none BUG=b:74600211 TEST=make buildall; Run cold-reset stress test over 3 days on grunt. No symptoms occurred. Change-Id: I5ad0c115da4254413d43269140eb71092c11b3b2 Signed-off-by: Mulin Chao Reviewed-on: https://chromium-review.googlesource.com/1134815 Reviewed-by: Jett Rink --- chip/npcx/registers.h | 1 + chip/npcx/system.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 94c34f34f6..be5f236a5b 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -889,6 +889,7 @@ enum { (NPCX_PMC_BASE_ADDR + 0x024)) #define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) #if defined(CHIP_FAMILY_NPCX7) +#define NPCX_FMUL_WIN_DLY REG8(NPCX_PMC_BASE_ADDR + 0x010) #define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + offset) #endif diff --git a/chip/npcx/system.c b/chip/npcx/system.c index c3cace0fb9..c6440134ad 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -722,6 +722,14 @@ void system_pre_init(void) */ system_mpu_config(); + /* + * Change FMUL_WIN_DLY from 0x8A to 0x81 for better WoV + * audio quality. + */ +#ifdef CHIP_FAMILY_NPCX7 + NPCX_FMUL_WIN_DLY = 0x81; +#endif + #ifdef CONFIG_CHIP_PANIC_BACKUP chip_panic_data_restore(); #endif -- cgit v1.2.1