From 49a586408762ca65edd6ecc277280cb1bddb5ccd Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Tue, 15 Feb 2022 13:46:16 +1100 Subject: nissa: update and regenerate GPIOs This fixes the default state for the power button GPIO (which was default-asserted) and updates the generated device tree files to reflect the current version of the pinmap CSV. BUG=b:203446068 TEST=zmake build nereid BRANCH=none Signed-off-by: Peter Marheine Change-Id: I243ef557d0d2f19e8129257818a263ada16dfa89 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3461049 Reviewed-by: Andrew McRae --- zephyr/projects/nissa/nereid_generated.dts | 10 +++++----- zephyr/projects/nissa/nissa.csv | 6 +++--- zephyr/projects/nissa/nivviks_generated.dts | 10 +++++----- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/zephyr/projects/nissa/nereid_generated.dts b/zephyr/projects/nissa/nereid_generated.dts index 971db9abd6..4b92b7a266 100644 --- a/zephyr/projects/nissa/nereid_generated.dts +++ b/zephyr/projects/nissa/nereid_generated.dts @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -67,6 +67,9 @@ gpios = <&gpioh 1 GPIO_INPUT>; enum-name = "GPIO_PACKET_MODE_EN"; }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; gpio_ec_prochot_odl: ec_prochot_odl { gpios = <&gpioi 1 GPIO_INPUT>; }; @@ -84,7 +87,7 @@ gpios = <&gpiod 6 GPIO_ODR_HIGH>; }; gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpiob 6 GPIO_ODR_LOW>; + gpios = <&gpiob 6 GPIO_ODR_HIGH>; enum-name = "GPIO_PCH_PWRBTN_L"; }; gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { @@ -99,9 +102,6 @@ gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { gpios = <&gpioe 5 GPIO_ODR_HIGH>; }; - gpio_ec_pch_wake_odl: ec_soc_wake_odl { - gpios = <&gpiob 2 GPIO_ODR_LOW>; - }; gpio_ec_wp_odl: ec_wp_odl { gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; }; diff --git a/zephyr/projects/nissa/nissa.csv b/zephyr/projects/nissa/nissa.csv index 0560d5aeed..0e91182567 100644 --- a/zephyr/projects/nissa/nissa.csv +++ b/zephyr/projects/nissa/nissa.csv @@ -89,7 +89,7 @@ ALL_SYS_PWRGD,POWER SEQUENCE,,IN,both,,N,3.30 V,,J11,B2,INPUT,,,Figure 398 PDG 0 PG_PP1050_MEM_S3_OD,POWER SEQUENCE,,IN,both,--,N,3.30 V,,D2,P5,INPUT,,??, PG_PP1050_PROC,POWER SEQUENCE,,IN,both,--,Y,3.30 V,,C2,A14,INPUT_PU,,??, SYS_RST_ODL,POWER SEQUENCE,Reset for SOC,OUT,,OD,N,3.30 V,SOC,H7,P4,OUTPUT_ODR,,, -EC_SOC_WAKE_ODL,POWER SEQUENCE,"Allows EC to wake AP (e.g., keyboard out of S0ix)",OUT,,OD,N,3.30 V,SOC,L11,E1,OUTPUT_ODL,GPIO_EC_PCH_WAKE_ODL,, +EC_PCH_WAKE_ODL,POWER SEQUENCE,"Allows EC to wake AP (e.g., keyboard out of S0ix)",OUT,,OD,N,3.30 V,SOC,L11,E1,OUTPUT_ODL,,EC_SOC_WAKE_ODL on schematic; software uses PCH_WAKE name, EC_SOC_RTCRST,POWER SEQUENCE,Allows EC to reset logic on the AP's RTC well,OUT,,TTL,N,3.30 V,SOC,J5,R2,OUTPUT,,, VCCIN_AUX_VID0,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L8,P2,INPUT,,, VCCIN_AUX_VID1,POWER SEQUENCE,Debug purposes,IN,both,,N,1.80 V,,L7,R1,INPUT,,, @@ -98,7 +98,7 @@ PWM_LED_1_ODL,PWM,LED 1,OUT,,PWM,N,3.30 V,,G8,P6,PWM_INVERT,,, PWM_LED_2_ODL,PWM,LED 2,OUT,,PWM,N,3.30 V,,G9,R7,PWM_INVERT,,, PWM_LED_3_ODL,PWM,LED 3,OUT,,PWM,N,3.30 V,,H10,P7,PWM_INVERT,,, EC_PSYS,PWM,System power monitoring output,OUT,,PWM,N,ANA,"Charger, IMVP9.1",G6,E15,OTHER,,, -EC_SOC_PWR_BTN_ODL,SOC,Buffered power button signal from EC to SOC,OUT,,OD,N,3.30 V,SOC,H9,J5,OUTPUT_ODL,GPIO_PCH_PWRBTN_L,, +EC_SOC_PWR_BTN_ODL,SOC,Buffered power button signal from EC to SOC,OUT,,OD,N,3.30 V,SOC,H9,J5,OUTPUT_ODR,GPIO_PCH_PWRBTN_L,, EC_SOC_HDMI_HPD,SOC,HPD buffer output for HDMI,OUT,,TTL,N,3.30 V,,L6,P15,OUTPUT,,, EC_PROCHOT_ODL,SOC,Allows us to send/read PROCHOT,I/O,both,OD,N,1.05 V,SOC,G3,H14,INPUT,,, EC_PCHHOT_ODL,SOC,Allows us to send/read PCHHOT,,,,,,,#N/A,#N/A,OTHER,,,Intel confirmed that this feature is not used. @@ -115,4 +115,4 @@ EN_USB_C0_CC2_VCONN,USB-PD,CC2 vconn en for IT81302 only,OUT,,TTL,N,3.30 V,,#N/A EC_TRIS_L,DEBUG,Debug for NPCX993,,,,,,,E4,#N/A,OTHER,,, EC_TEST_L,DEBUG,Debug for NPCX994,,,,,,,K2,#N/A,OTHER,,, EC_32KXOUT,DEBUG,Debug for NPCX995,,,,,,,M5,#N/A,OTHER,,, -EC_SHDF_ESPI_L,DEBUG,Debug for NPCX996,,,,,,,H3,#N/A,OTHER,,, +EC_SHDF_ESPI_L,DEBUG,Debug for NPCX996,,,,,,,H3,#N/A,OTHER,,, \ No newline at end of file diff --git a/zephyr/projects/nissa/nivviks_generated.dts b/zephyr/projects/nissa/nivviks_generated.dts index 1c6e8134c6..4a0e66f10d 100644 --- a/zephyr/projects/nissa/nivviks_generated.dts +++ b/zephyr/projects/nissa/nivviks_generated.dts @@ -1,4 +1,4 @@ -/* Copyright 2021 The Chromium OS Authors. All rights reserved. +/* Copyright 2022 The Chromium OS Authors. All rights reserved. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -63,6 +63,9 @@ gpios = <&gpio1 7 GPIO_OUTPUT>; enum-name = "GPIO_KBD_KSO2"; }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 0 GPIO_ODR_LOW>; + }; gpio_ec_prochot_odl: ec_prochot_odl { gpios = <&gpiof 1 GPIO_INPUT>; }; @@ -80,7 +83,7 @@ gpios = <&gpio7 2 GPIO_ODR_HIGH>; }; gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { - gpios = <&gpioc 1 GPIO_ODR_LOW>; + gpios = <&gpioc 1 GPIO_ODR_HIGH>; enum-name = "GPIO_PCH_PWRBTN_L"; }; gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { @@ -95,9 +98,6 @@ gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { gpios = <&gpioa 4 GPIO_ODR_HIGH>; }; - gpio_ec_pch_wake_odl: ec_soc_wake_odl { - gpios = <&gpiob 0 GPIO_ODR_LOW>; - }; gpio_ec_wp_odl: ec_wp_odl { gpios = <&gpioa 1 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; }; -- cgit v1.2.1