From 53b6a345c8f7fecd8c8f8ea1e23870308dafdf44 Mon Sep 17 00:00:00 2001 From: Todd Broch Date: Thu, 11 Sep 2014 15:42:38 -0700 Subject: hoho: Enable USB PD support. CL to allow hoho to receive initial USB PD communication (source capabilities payload). BRANCH=none BUG=chrome-os-partner:31192 TEST=manual, When attaching hoho to fruitpie and configured via 'pd dualrole source' I see on hoho side: --- UART initialized after reboot --- [Reset cause: reset-pin power-on] [Image: RO, hoho_v1.1.2213-2bf6a29-dirty 2014-09-15 12:10:22 tbroch@brisket.mtv.corp.google.com] [0.000466 Inits done] C0 st2 Console is enabled; type HELP for help. > [0.250678 USB PD initialized] C0 st3 [0.264629 PD TMOUT RX 1/1] RX ERR (-1) Request [1] 5V 3000mA C0 st4 C0 st5 C0 st6 > pd 0 state Port C0, Enabled - Role: SNK Polarity: CC2 State: SNK_READY Change-Id: Ic5871946425f0ff12d717fbbbbb9e81c6b67cc6f Signed-off-by: Todd Broch Reviewed-on: https://chromium-review.googlesource.com/217977 Reviewed-by: Alec Berg --- board/hoho/board.h | 5 +- board/hoho/build.mk | 1 + board/hoho/ec.tasklist | 3 +- board/hoho/usb_pd_config.h | 140 +++++++++++++++++++++++++++++++++++++++++++++ board/hoho/usb_pd_policy.c | 90 +++++++++++++++++++++++++++++ 5 files changed, 237 insertions(+), 2 deletions(-) create mode 100644 board/hoho/usb_pd_config.h create mode 100644 board/hoho/usb_pd_policy.c diff --git a/board/hoho/board.h b/board/hoho/board.h index 54b75c9a33..405116e698 100644 --- a/board/hoho/board.h +++ b/board/hoho/board.h @@ -19,11 +19,15 @@ #define CONFIG_ADC #define CONFIG_BOARD_PRE_INIT #define CONFIG_CMD_SPI_FLASH +#define CONFIG_HW_CRC #define CONFIG_I2C #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SIZE 1048576 #define CONFIG_SPI_MASTER_PORT 2 #define CONFIG_SPI_CS_GPIO GPIO_PD_MCDP_SPI_CL_L +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_INTERNAL_COMP #undef CONFIG_WATCHDOG_HELP #undef CONFIG_LID_SWITCH #undef CONFIG_TASK_PROFILING @@ -40,7 +44,6 @@ #ifndef __ASSEMBLER__ /* Timer selection */ -#define TIM_CLOCK_PD_RX 1 #define TIM_CLOCK32 2 #define TIM_ADC 3 diff --git a/board/hoho/build.mk b/board/hoho/build.mk index 83b8716734..92bb84b52c 100644 --- a/board/hoho/build.mk +++ b/board/hoho/build.mk @@ -11,3 +11,4 @@ CHIP_FAMILY:=stm32f0 CHIP_VARIANT:=stm32f07x board-y=board.o +board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/board/hoho/ec.tasklist b/board/hoho/ec.tasklist index 8ff4e8234b..e9c8c1cc1f 100644 --- a/board/hoho/ec.tasklist +++ b/board/hoho/ec.tasklist @@ -18,4 +18,5 @@ */ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) + TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE) diff --git a/board/hoho/usb_pd_config.h b/board/hoho/usb_pd_config.h new file mode 100644 index 0000000000..4abb3e8d51 --- /dev/null +++ b/board/hoho/usb_pd_config.h @@ -0,0 +1,140 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* USB Power delivery board configuration */ + +#ifndef __USB_PD_CONFIG_H +#define __USB_PD_CONFIG_H + +/* Port and task configuration */ +#define PD_PORT_COUNT 1 +#define PORT_TO_TASK_ID(port) TASK_ID_PD +#define TASK_ID_TO_PORT(id) 0 + +/* Timer selection for baseband PD communication */ +#define TIM_CLOCK_PD_TX_C0 17 +#define TIM_CLOCK_PD_RX_C0 1 + +#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0 +#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0 + +/* Timer channel */ +#define TIM_RX_CCR_C0 1 + +/* RX timer capture/compare register */ +#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0)) +#define TIM_RX_CCR_REG(p) TIM_CCR_C0 + +/* TX and RX timer register */ +#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0)) +#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0)) +#define TIM_REG_TX(p) TIM_REG_TX_C0 +#define TIM_REG_RX(p) TIM_REG_RX_C0 + +/* use the hardware accelerator for CRC */ +#define CONFIG_HW_CRC + +/* TX is using SPI1 on PB3-4 */ +#define SPI_REGS(p) STM32_SPI1_REGS + +static inline void spi_enable_clock(int port) +{ + STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1; +} + +/* SPI1_TX no remap needed */ +#define DMAC_SPI_TX(p) STM32_DMAC_CH3 + +/* RX is using COMP1 triggering TIM1 CH1 */ +#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1 +#define CMP2OUTSEL 0 + +#define TIM_CCR_IDX(p) TIM_RX_CCR_C0 +#define TIM_CCR_CS 1 +#define EXTI_COMP_MASK(p) (1 << 21) +#define IRQ_COMP STM32_IRQ_COMP +/* triggers packet detection on comparator falling edge */ +#define EXTI_XTSR STM32_EXTI_FTSR + +/* TIM1_CH1 no remap needed */ +#define DMAC_TIM_RX(p) STM32_DMAC_CH2 + +/* the pins used for communication need to be hi-speed */ +static inline void pd_set_pins_speed(int port) +{ + /* 40 Mhz pin speed on TX_EN (PA15) */ + STM32_GPIO_OSPEEDR(GPIO_A) |= 0xC0000000; + /* 40 MHz pin speed on SPI CLK/MOSI (PB3/4) TIM17_CH1 (PB9) */ + STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C03C0; +} + +/* Reset SPI peripheral used for TX */ +static inline void pd_tx_spi_reset(int port) +{ + /* Reset SPI1 */ + STM32_RCC_APB2RSTR |= (1 << 12); + STM32_RCC_APB2RSTR &= ~(1 << 12); +} + +/* Drive the CC line from the TX block */ +static inline void pd_tx_enable(int port, int polarity) +{ + /* PB4 is SPI1_MISO */ + gpio_set_alternate_function(GPIO_B, 0x0010, 0); + + gpio_set_level(GPIO_PD_CC1_TX_EN, 1); +} + +/* Put the TX driver in Hi-Z state */ +static inline void pd_tx_disable(int port, int polarity) +{ + /* output low on SPI TX (PB4) to disable the FET */ + STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) + & ~(3 << (2*4))) + | (1 << (2*4)); + /* put the low level reference in Hi-Z */ + gpio_set_level(GPIO_PD_CC1_TX_EN, 0); +} + +static inline void pd_select_polarity(int port, int polarity) +{ + /* + * use the right comparator : CC1 -> PA1 (COMP1 INP) + * use VrefInt / 2 as INM (about 600mV) + */ + STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK) + | STM32_COMP_CMP1EN | STM32_COMP_CMP1INSEL_VREF12; +} + +/* Initialize pins used for TX and put them in Hi-Z */ +static inline void pd_tx_init(void) +{ + gpio_config_module(MODULE_USB_PD, 1); +} + +static inline void pd_set_host_mode(int port, int enable) {} + +static inline int pd_adc_read(int port, int cc) +{ + return adc_read_channel(ADC_CH_CC1_PD); +} + +static inline int pd_snk_is_vbus_provided(int port) +{ + return 1; +} + +/* 3.0A DFP : no-connect voltage is 2.45V */ +#define PD_SRC_VNC 2450 /* mV */ + +/* UFP-side : threshold for DFP connection detection */ +#define PD_SNK_VA 250 /* mV */ + +/* we are acting only as a sink */ +#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED + +/* delay necessary for the voltage transition on the power supply */ +#define PD_POWER_SUPPLY_TRANSITION_DELAY 50000 /* us */ +#endif /* __USB_PD_CONFIG_H */ diff --git a/board/hoho/usb_pd_policy.c b/board/hoho/usb_pd_policy.c new file mode 100644 index 0000000000..57099a960d --- /dev/null +++ b/board/hoho/usb_pd_policy.c @@ -0,0 +1,90 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "adc.h" +#include "board.h" +#include "common.h" +#include "console.h" +#include "gpio.h" +#include "hooks.h" +#include "registers.h" +#include "task.h" +#include "timer.h" +#include "util.h" +#include "usb_pd.h" + +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +/* Source PDOs */ +const uint32_t pd_src_pdo[] = {}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +/* Fake PDOs : we just want our pre-defined voltages */ +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, 0), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +/* Desired voltage requested as a sink (in millivolts) */ +static unsigned select_mv = 5000; + +int pd_choose_voltage(int cnt, uint32_t *src_caps, uint32_t *rdo) +{ + int i; + int ma; + int set_mv = select_mv; + + /* Default to 5V */ + if (set_mv <= 0) + set_mv = 5000; + + /* Get the selected voltage */ + for (i = cnt; i >= 0; i--) { + int mv = ((src_caps[i] >> 10) & 0x3FF) * 50; + int type = src_caps[i] & PDO_TYPE_MASK; + if ((mv == set_mv) && (type == PDO_TYPE_FIXED)) + break; + } + if (i < 0) + return -EC_ERROR_UNKNOWN; + + /* request all the power ... */ + ma = 10 * (src_caps[i] & 0x3FF); + *rdo = RDO_FIXED(i + 1, ma, ma, 0); + ccprintf("Request [%d] %dV %dmA\n", i, set_mv/1000, ma); + return ma; +} + +void pd_set_input_current_limit(uint32_t max_ma) +{ + /* No battery, nothing to do */ + return; +} + +void pd_set_max_voltage(unsigned mv) +{ + select_mv = mv; +} + +int requested_voltage_idx; +int pd_request_voltage(uint32_t rdo) +{ + return EC_SUCCESS; +} + +int pd_set_power_supply_ready(int port) +{ + return EC_SUCCESS; +} + +void pd_power_supply_reset(int port) +{ +} + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + -- cgit v1.2.1