From 64101de32237448278da4d668291b73779c0b46b Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 Aug 2013 09:00:08 -0700 Subject: bolt: force SYS_PWROK and PP3300_DSW_GATED_EN to 0 in forcing G3 path The following signals were not being initialized properly in the forcing G3 path: - GPIO_SYS_PWROK - GPIO_PP3300_DSW_GATED_EN This lead to the EC RW sysjump, but the boards wouldn't reboot on the x86 side. Sadly, without this change, the board I have works. However, those signals need to be driven low. BUG=chrome-os-partner:20372 BRANCH=None TEST=Willis tested on boards that previously didn't work. Original-Change-Id: I1771881485bc5be73ed2b08da91fddff9ab09167 Signed-off-by: Aaron Durbin Reviewed-on: https://gerrit.chromium.org/gerrit/63845 Reviewed-by: Randall Spangler (cherry picked from commit 706f1211468ebfcd0fc9890b83f8443994a9f7f0) Change-Id: Ia24fbfc09dc7d4196e2118427e994086bcc5e00e Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/64219 --- board/bolt/power_sequence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/bolt/power_sequence.c b/board/bolt/power_sequence.c index bca948a596..ba5e70589c 100644 --- a/board/bolt/power_sequence.c +++ b/board/bolt/power_sequence.c @@ -127,11 +127,13 @@ enum x86_state x86_chipset_init(void) /* Force all signals to their G3 states */ CPRINTF("[%T x86 forcing G3]\n"); gpio_set_level(GPIO_PCH_PWROK, 0); + gpio_set_level(GPIO_SYS_PWROK, 0); gpio_set_level(GPIO_VCORE_EN, 0); gpio_set_level(GPIO_PP1050_EN, 0); gpio_set_level(GPIO_PP1350_EN, 0); gpio_set_level(GPIO_EC_EDP_VDD_EN, 0); gpio_set_level(GPIO_PP3300_DX_EN, 0); + gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0); gpio_set_level(GPIO_PP5000_EN, 0); gpio_set_level(GPIO_PCH_DPWROK, 0); wireless_enable(0); -- cgit v1.2.1